Automated technique for design of NoC with minimal communication latency

Contention-free and Application-specific Network-on-Chip Generation for Embedded Systems

“…Every graph has 20-30 tasks, 15-30 messages and 5-9 allocated PEs. Such approach reminds also the one presented in (Leary et al 2009), but is far chip resource conserving -no routers without PE are allowed. The first one ranges from 0,36 (communication-oriented system) to 1,83 (calculation-oriented system with less probability of message contention).…”

“…TDMA method allows for packets interleaving and demand very careful scheduling (at the level of single flits instead of packets). The drawbacks of the bandwidth-based approach, based on Integer Linear Programming, for application-to-NoC mapping is demonstrated in (Leary et al 2009). Scheduling policy permits non-optimal routes and irregular topologies (Stuijk et al 2008) or is restricted to shortest paths and regular networks (e.g.…”

Automated synthesis of custom networks-on-chip for real world applications

“…The accepted base topology is not shown here due to paucity of space. However, assuming that the green lines are selected, the new clock domain for router ID [8] is clock_1, along with changes in bridge connectivity which reduce the three transitions between {c0, ID [8]}, {m1, ID [11]} and {ID [11], ID [17]} to two between {m0, ID [8]} and {s0, ID [14]}. This reduces latency as well since asynchronous crossing requires more cycles for transitioning the domain.…”

Application-Specific Heterogeneous Network-on-Chip Design

“…For custom NoCs and irregular mesh, a core graph, which describes the communication among different cores, is needed for floor-planning. Min-cut partitioning on the task graph is explored by Leary et al [26], who produce a floor-planning-aware core graph.…”