Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis

Vasicek, Zdenek; Mrazek, Vojtech; Sekanina, Lukas

doi:10.23919/date58400.2024.10546795

2024 Design, Automation &Amp;amp; Test in Europe Conference &Amp;amp; Exhibition (DATE) 2024

DOI: 10.23919/date58400.2024.10546795

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Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis

Zdenek Vasicek,

Vojtech Mrazek,

Lukas Sekanina

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Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis

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