Automatic Code-Transformation and Architecture Refinement for Application-Specific Multiprocessor SoCs with Shared Memory

Abstract

Memory represents a major bottleneck in embedded systems. For multimedia applications bulky of data in these embedded systems require shared memory. But the integration of this kind of memory implies some architectural modifications and code transformations. And no automatic tool exists allowing designers to integrate shared memory in the SoC design flow. In this work, we present a systematic approach for the design of shared memory architectures for application-specific multiprocessor systems-on-chip. This work focuses on the code-transformations related to the integration of a shared memory.

Application-Specific Heterogeneous Network-on-Chip Design

“…MPSoCs [31,32] has become popular due to its promising architecture combining different types of processing cores, networking elements, memory components and other hardware subsystems on a single chip. One of the major distinctions of MPSoC technology is its communication architecture.…”

A memory-conscious code parallelization scheme

“…In the first category are the efforts on designing a suitable memory hierarchy for chip multiprocessors. Examples of the studies in this category include [9] and [10]. While in [9] the authors propose methods for optimal memory space partitioning for a given embedded application, in [10] they study architectural refinements for shared memory chip multiprocessors.…”