Automatic Design of Area-Efficient Configurable ASIC Cores

Compton, Katherine; Hauck, Scott

doi:10.1109/tc.2007.1035

Cited by 32 publications

(31 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Compton and Hauck [11] have also measured the area differences between FPGA and standard cell designs. They implemented multiple circuits from eight different application domains, including areas such as radar and image processing, on the Xilinx Virtex-II FPGA, in standard cells on a 0.18 µm CMOS process from TSMC, and on a custom configurable platform.…”

Section: Past Fpga To Asic Comparisonsmentioning

confidence: 99%

Measuring the Gap Between FPGAs and ASICs

Kuon

Rose

2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

795

132

View full text Add to dashboard Cite

This paper presents experimental measurements of the differences between a 90nm CMOS FPGA and 90nm CMOS Standard Cell ASICs in terms of logic density, circuit speed and power consumption. We are motivated to make these measurements to enable system designers to make better informed choices between these two media and to give insight to FPGA makers on the deficiencies to attack and thereby improve FPGAs. In the paper, we describe the methodology by which the measurements were obtained and we show that, for circuits containing only combinational logic and flipflops, the ratio of silicon area required to implement them in FPGAs and ASICs is on average 40. Modern FPGAs also contain "hard" blocks such as multiplier/accumulators and block memories and we find that these blocks reduce this average area gap significantly to as little as 21. The ratio of critical path delay, from FPGA to ASIC, is roughly 3 to 4, with less influence from block memory and hard multipliers. The dynamic power consumption ratio is approximately 12 times and, with hard blocks, this gap generally becomes smaller.

show abstract

Section: Past Fpga To Asic Comparisonsmentioning

confidence: 99%

Measuring the Gap Between FPGAs and ASICs

Kuon

Rose

2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

795

132

View full text Add to dashboard Cite

show abstract

“…Heterogeneous coarse-grain reconfigurable devices have been researched extensively in the RaPiD project [19], [20], [21]. The result of this work has been a tool that generates device architectures, and the most recent work compares RaPiD architectures to standard-cell ASICs and FPGAs.…”

Section: Related Workmentioning

confidence: 99%

“…To prevent the regions of different resource types overlapping, clearly a iq > b jr or a jr > b iq . These constraints can be represented in a mathematical program by introducing two binary variables δ qr1 and δ qr2 as in (18)(19)(20)(21). The equations described here have been extended to account for the different region types.…”

Section: Representing An Architecture In the Ilpmentioning

confidence: 99%

“…The number of binary modelling node-node placement δ uvx (12-17) is 2n nodes (n nodes − 1), where n nodes is the number of nodes in a given benchmark circuit. Similarly, the number of binary variables representing the floorplan of the underlying architecture δ qrx (18)(19)(20)(21) is n regions (n regions − 1), where n regions is the number of regions. Finally, the number of binary variables representing the floorplanning of nodes onto the architecture δ uir (22)(23)(24) is at most 2n nodes n regions .…”

Section: Heuristic Determination Of Reconfigurable Architecturesmentioning

confidence: 99%

“…As the number of regions allowed on the device is increased, so is the number of binary variables related to floorplanning of regions, δ qrx (18)(19)(20)(21), and binary variables related to the placement of nodes within regions, δ uir . If these variables are left to the ILP solving software to determine, a single run of the partially relaxed ILP can take over one hour, and given that the entire procedure takes over 500 iterations for the benchmark set used in our experiments, such an approach is not appropriate.…”

Section: A Achieving a Scalable Run-time Using Clusteringmentioning

confidence: 99%

See 2 more Smart Citations

Integrated Floorplanning, Module-Selection, and Architecture Generation for Reconfigurable Devices

Smith

Constantinides

Cheung

2008

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

Abstract-This paper is concerned with the application of formal optimisation methods to the design of mixed-granularity FPGAs. In particular, we investigate the appropriate mix and floorplan of heterogeneous elements: multipliers, RAMs, and LUT-based logic, in order to maximise the performance of a set of DSP benchmark applications, given a fixed silicon budget. A mathematical programming framework is introduced, along with a set of heuristics, capable of providing upper-bounds on the achievable reconfigurable-to-fixed-logic performance ratio. Moreover, we use linear-programming bounding procedures from the operations research community to provide lower-bounds on the same quantity. Our results provide, for the first time, quantifications of the optimal performance/area-enhancing capability of multipliers and RAM blocks within a system context. The approach detailed provides a formal mechanism to explore future technology nodes.

show abstract

A Survey of Coarse-Grain Reconfigurable Architectures and Cad Tools

Theodoridis¹,

Soudris²,

Vassiliadis³

Fine- And Coarse-Grain Reconfigurable Computing

View full text Add to dashboard Cite

According to the granularity of configuration, reconfigurable systems are classified in two categories, which are the fine-and coarse-grain ones. The purpose of this chapter is to study the features of coarse-grain reconfigurable systems, to examine their advantages and disadvantages, to discuss critical design issues that must be addressed during their development, and to present representative coarsegrain reconfigurable systems that have been proposed in the literature.Current and future applications are characterized by different features and demands, which increase the complexity of developing systems to implement them. The majority of contemporary applications, for instance DSP or multimedia ones, are characterized by the existence of computationally-intensive algorithms. Also, high speed and throughput are frequently needed since real-time applications (e.g. video conferencing) are widely-supported by modern systems. Moreover, due to the wide spread of portable devices (e.g. laptops, mobile phones), low-power consumption becomes an emergency need. In addition, electronic systems, for instance, consumer electronics may have strict size constraints, which make the silicon area a critical Controller CGRU CGRU CGRU CGRU CGRU CGRU Programmable Interconnections Config. Mem.

show abstract

Automatic Design of Area-Efficient Configurable ASIC Cores

Cited by 32 publications

References 14 publications

Measuring the Gap Between FPGAs and ASICs

Measuring the Gap Between FPGAs and ASICs

Integrated Floorplanning, Module-Selection, and Architecture Generation for Reconfigurable Devices

A Survey of Coarse-Grain Reconfigurable Architectures and Cad Tools

Contact Info

Product

Resources

About