Automatic extraction of functional parallelism from ordinary programs

High-Level Verification

2011

Abstract-The growing complexity of systems and their implementation into silicon encourages designers to look for ways to model designs at higher levels of abstraction and then incrementally build portions of these designs-automatically or manually-from these high-level specifications. Unfortunately, this translation process itself can be buggy, which can create a mismatch between what a designer intends and what is actually implemented in the circuit. Therefore, checking if the implementation is a refinement or equivalent to its initial specification is of tremendous value. In this paper, we present an approach to automatically validate the implementation against its initial high-level specification using insights from translation validation, automated theorem proving, and relational approaches to reasoning about programs. In our experiments, we first focus on concurrent systems modeled as communicating sequential processes and show that their refinements can be validated using our approach. Next, we have applied our validation approach to a realistic scenario-a parallelizing high-level synthesis framework called Spark. We present the details of our algorithm and experimental results.

Section: B Spark: Hls Frameworkmentioning

confidence: 99%

Translation Validation of High-Level Synthesis

Kundu

Lerner

High-Level Verification

2011

“…A sequence of scheduling steps with no control flow between them is encapsulated in a basic block. We capture the control flow between basic blocks using a hierarchical intermediate representation called hierarchical task graphs (HTGs) [15,16]. HTGs model the design with three type of nodes: (a) single nodes that encapsulate basic blocks, (b) compound nodes that are hierarchical in nature and encapsulate conditional constructs such as if-then-else blocks and switch-case blocks, and (c) loop nodes that encapsulate for-loops, while-loops etc.…”

Section: Model and Terminologymentioning

confidence: 99%

Dynamically increasing the scope of code motions during the high-level synthesis of digital circuits

Dutt

IEE Proc., Comput. Digit. Tech.

et al. 2003

The quality of high-level synthesis results for designs with complex and nested conditionals and loops can be improved significantly by employing speculative code motions. Two techniques are presented that add scheduling steps to the branch of a conditional construct with fewer scheduling steps. This 'balances' or equalises the number of scheduling steps in the conditional branches and increases the scope for application of speculative code motions. These branch balancing techniques have been applied 'dynamically' during scheduling. The authors have implemented algorithms for dynamic branch balancing techniques in a C-to-VHDL high-level synthesis framework called Spark. The utility of these techniques is demonstrated by experimental results on four designs derived from two moderately complex applications, namely, MPEG-1 and the GIMP image processing tool. These results show that the two branch balancing techniques can reduce the cycles on the longest path through the design by up to 38% and the number of states in the controller by up to 37%.

Euro-Par’98 Parallel Processing

“…The compiler applies control and data dependence analysis to produce an intermediate program representation called the Hierarchical Task Graph (HTG) [5]. Programs are represented with a hierarchical structure consisting of simple and compound nodes.…”

Section: Autoscheduling and Performance Limitationsmentioning

confidence: 99%

Enhancing the performance of autoscheduling in Distributed Shared Memory multiprocessors

Nikolopoulos

Polychronopoulos

Papatheodorou

1998

Abstract. Autoscheduling is a parallel program compilation and execution model that combines uniquely three features: Automatic extraction of loop and functional parallelism at any level of granularity, dynamic scheduling of parallel tasks, and dynamic program adaptability on multiprogrammed shared memory multiprocessors. This paper presents a technique that enhances the performance of autoscheduling in Distributed Shared Memory (DSM) multiprocessors, targetting mainly at medium and large scale systems, where poor data locality and excessive communication impose performance bottlenecks. Our technique partitions the application Hierarchical Task Graph and maps the derived partitions to clusters of processors in the DSM architecture. Autoscheduling is then applied separately for each partition to enhance data locality and reduce communication costs. Our experimental results show that partitioning achieves remarkable performance improvements compared to a standard autoscheduling environment and a commercial parallelizing compiler.