Wireless Telecommunications Symposium 2012 2012
DOI: 10.1109/wts.2012.6266106
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Automatic Gain Control on FPGA for Software-Defined Radios

Abstract: This paper introduces an efficient implementation of the Automatic Gain Control (AGC) for an IEEE 802.15.3c compliant receiver developed using a Field-Programmable Gate Arrays (FPGAs), both feed-forward and feed-backward AGCs are designed, implemented and evaluated.

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Cited by 9 publications
(2 citation statements)
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“…Therefore, the AGC is implemented in the FPGA on board the radio to minimize latency. The implemented AGC is inspired by [ 17 , 29 ].…”
Section: Measurement Systemmentioning
confidence: 99%
“…Therefore, the AGC is implemented in the FPGA on board the radio to minimize latency. The implemented AGC is inspired by [ 17 , 29 ].…”
Section: Measurement Systemmentioning
confidence: 99%
“…The problem of unstable signal power range [14][15]. In the past, most of the literature was on the automatic gain control algorithm, but the research on the automatic gain control system of the DRU digital domain signal power in the DAS system is relatively lacking [16][17][18][19][20][21]. This paper based on the difference between the uplink and downlink data links in the DRU Among them, the automatic power control (APC) system is researched and optimized, and board-level verification is based on FPGA In order to meet the requirement of no overflow of bit width and stable output power after carrier combining in DRU, this paper controls the power of uplink and downlink of DRU based on FPGA by counting signal power values in different time lengths.…”
Section: Introductionmentioning
confidence: 99%