Automatic generation of assertions from system level design using data mining

Liu, Lingyi; Sheridan, David; Athavale, Viraj; Vasudevan, Shobha

doi:10.1109/memcod.2011.5970526

Cited by 14 publications

(8 citation statements)

References 17 publications

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“…A liveness assumption is then computed by putting fairness assumptions on the remaining edges. Liu et al [21] mine counterexamples to realizability to find new assumptions. A key difference between the assumptions generated in these approaches and the assumptions of this paper is that we compute assumptions for the existence of dominant strategies, not for the existence of winning strategies.…”

Section: Related Workmentioning

confidence: 99%

What You Really Need To Know About Your Neighbor

Damm¹,

Finkbeiner²,

Rakow³

2016

Electron. Proc. Theor. Comput. Sci.

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A fundamental question in system design is to decide how much of the design of one component must be known in order to successfully design another component of the system. We study this question in the setting of reactive synthesis, where one constructs a system implementation from a specification given in temporal logic. In previous work, we have shown that the system can be constructed compositionally, one component at a time, if the specification admits a "dominant" (as explained in Introduction) strategy for each component. In this paper, we generalize the approach to settings where dominant strategies only exist under certain assumptions about the future behavior of the other components. We present an incremental synthesis method based on the automatic construction of such assumptions.

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Section: Related Workmentioning

confidence: 99%

What You Really Need To Know About Your Neighbor

Damm¹,

Finkbeiner²,

Rakow³

2016

Electron. Proc. Theor. Comput. Sci.

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show abstract

“…it covers all functionalities of the device) [15]. In order to help designers with the verification process, methodologies and tools have been developed which automatically generate assertions from simulation traces of an implementation of the device [22,32,8,7]. The objective is to provide a small set of assertions that cover all behaviors of the device, in order to extend the basic manually-defined set of assertions.…”

Section: Introductionmentioning

confidence: 99%

Pattern Discovery in Colored Strings

Lipták

Puglisi

Rossi

2020

ACM J. Exp. Algorithmics

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In this article, we consider the problem of identifying patterns of interest in colored strings. A colored string is a string where each position is assigned one of a finite set of colors. Our task is to find substrings of the colored string that always occur followed by the same color at the same distance. The problem is motivated by applications in embedded systems verification, in particular, assertion mining. The goal there is to automatically find properties of the embedded system from the analysis of its simulation traces. We show that, in our setting, the number of patterns of interest is upper-bounded by O ( n 2 ), where n is the length of the string. We introduce a baseline algorithm, running in O ( n 2 ) time, which identifies all patterns of interest satisfying certain minimality conditions for all colors in the string. For the case where one is interested in patterns related to one color only, we also provide a second algorithm that runs in O ( n 2 log n ) time in the worst case but is faster than the baseline algorithm in practice. Both solutions use suffix trees, and the second algorithm also uses an appropriately defined priority queue, which allows us to reduce the number of computations. We performed an experimental evaluation of the proposed approaches over both synthetic and real-world datasets, and found that the second algorithm outperforms the first algorithm on all simulated data, while on the real-world data, the performance varies between a slight slowdown (on half of the datasets) and a speedup by a factor of up to 11.

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“…RELATED WORK Researchers at university of Illinois have introduced a new methodology for generating RTL assertions automatically called GoldMine [9]. They extended the new methodology for system level assertions in [10]. GoldMine is based on decision tree mining and static analysis, where the generated assertions are validated by a formal verification engine [11].…”

Section: Introductionmentioning

confidence: 99%

Complete Properties Extraction from Simulation Traces for Assertions Auto-generation

Hanafy¹,

Said

Wahba

2015

2015 IEEE 24th North Atlantic Test Workshop

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Machine learning techniques based on Data Mining are employed for automatic assertion generation in hardware digital design verification. This paper presents a new mining technique to extract all design properties from simulation traces. The extracted properties cover all possible design assertions either at system level or Register Transfer Logic (RTL) verification depending on the simulated design level. It can afterwards be tuned or filtered to match a certain desired abstraction level. The new technique is based on a Breadth-First Decision Tree (BF-DT) search algorithm. The innovated algorithm maps the input simulation traces to a search tree that covers all possible input combinations, and prunes the redundant paths. The proposed technique is tested against recently innovated mining techniques for some basic digital design functions as a proof of concept for the gained efficiency. The main advantage of the new technique is the possibility to extract all the design properties from the simulation traces achieving hundred-percent coverage in a reasonably efficient time for millions of simulation traces.

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Automatic generation of assertions from system level design using data mining

Cited by 14 publications

References 17 publications

What You Really Need To Know About Your Neighbor

What You Really Need To Know About Your Neighbor

Pattern Discovery in Colored Strings

Complete Properties Extraction from Simulation Traces for Assertions Auto-generation

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