Automatic generation of instruction sequences targeting hard-to-detect structural faults in a processor

2010 IEEE International Test Conference

Gizopoulos³

et al. 2010

Section: Sbst Of Single-threaded Processorsmentioning

confidence: 99%

MT-SBST: Self-test optimization in multithreaded multicore architectures

Foutris

2010 IEEE International Test Conference

Gizopoulos³

et al. 2010

“…Instruction-based online periodic testing comes more natural since the processor stays in normal operating mode during self-test. The microprocessors' instruction-based self-testing for manufacturing testing has been thoroughly investigated in [8], [9], [10], [11], [12], [13], and [14] and for online periodic testing in [15], [16], and [17]. In [15], the authors present the key requirements of efficient periodic instruction-based self-testing, namely, high fault coverage, small memory footprint, low execution time, and low power consumption.…”

Section: Introductionmentioning

confidence: 99%

Instruction-Based Online Periodic Self-Testing of Microprocessors with Floating-Point Units

Xenoulis

Gizopoulos

IEEE Trans. Dependable and Secure Comput.

et al. 2009

Online periodic testing of microprocessors is a valuable means to increase the reliability of a low-cost system, when neither hardware nor time redundant protection schemes can be applied. This is particularly valid for floating-point (FP) units, which are becoming more common in embedded systems and are usually protected from operational faults through costly hardware redundant approaches. In this paper, we present scalable instruction-based self-test program development for both single and double precision FP units considering different instruction sets (MIPS, PowerPC, and Alpha), different microprocessor architectures (32/64-bit architectures) and different memory configurations. Moreover, we introduce bit-level manipulation instruction sequences that are essential for the development of FP unit's self-test programs. We developed self-test programs for single and double precision FP units on 32-bit and 64-bit microprocessor architectures and evaluated them with respect to the requirements of low-cost online periodic self-testing: fault coverage, memory footprint, execution time, and power consumption, assuming different memory hierarchy configurations. Our comprehensive experimental evaluations reveal that the instruction set architecture plays a significant role in the development of self-test programs. Additionally, we suggest the most suitable self-test program development approach when memory footprint or low power consumption is of paramount importance.

“…Several SBST approaches and case studies have been proposed in the literature [2]- [13]. Two major microprocessor vendors, namely Intel [4] and Sun [5], have used SBST in order to effectively utilize low-cost test equipment in the microprocessor manufacturing flow.…”

Section: Introductionmentioning

confidence: 99%

“…Other SBST approaches [6]- [13] are structural in nature. Most of these approaches have been applied either to low-complexity processor models (short word length, simple functional units, without pipelining), or to selected functional modules in complex processors.…”

Section: Introductionmentioning

confidence: 99%

Systematic Software-Based Self-Test for Pipelined Processors

Gizopoulos

Hatzimihail

et al. 2008

IEEE Trans. VLSI Syst.

Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in systems-on-chip (SoCs). By moving test related functions from external resources to the SoC's interior, in the form of test programs that the on-chip processor executes, SBST significantly reduces the need for high-cost, big-iron testers, and enables high-quality at-speed testing and performance binning. Thus far, SBST approaches have focused almost exclusively on the functional (programmer visible) components of the processor. In this paper, we analyze the challenges involved in testing an important component of modern processors, namely, the pipelining logic, and propose a systematic SBST methodology to address them. We first demonstrate that SBST programs that only target the functional components of the processor are not sufficient to test the pipeline logic, resulting in a significant loss of overall processor fault coverage. We further identify the testability hotspots in the pipeline logic using two fully pipelined reduced instruction set computer (RISC) processor benchmarks. Finally, we develop a systematic SBST methodology that enhances existing SBST programs so that they comprehensively test the pipeline logic. The proposed methodology is complementary to previous SBST techniques that target functional components (their results can form the input to our methodology, and thus we can reuse the test development effort behind preexisting SBST programs). We automate our methodology and incorporate it in an integrated software environment (developed using Java, XML, and archC) for the automatic generation of SBST routines for microprocessors. We apply the methodology to the two complex benchmark RISC processors with respect to two fault models: stuck-at fault model and transition delay fault model. Simulation results show that our methodology provides significant improvements for the two fault models, both for the entire processor (12% fault coverage improvement on average) and for the pipeline logic itself (19% fault coverage improvement on average), compared to a conventional SBST approach.