A repairable memory cell consists of repair logic and a memory repair register (MRR) which holds the signature for memory repair. Every time a repairable memory is powered on, the memory repair register is programmed by transferring the memory repair signature from a nonvolatile memory such an EPROM into MRR. During repair signature programming, the MRR of all memories in the design are wired together to load the signature in a serial fashion. For example, if there are three memories in the design with an 8 bit MRR each, then each of these three MRR's will be configured to shift in a 24-bit signature in a serial fashion. During the course of normal operation, memories are frequently shutdown to reduce power consumption, while some part of the design remains operational. When these memories are powered back on, the MRR's must be reprogrammed for proper memory operation. This work provides an elegant mechanism to hold these MRR signatures in a shadow register which can later be used to reprogram the MRR to make the memories operational. The method provides a mechanism for loading each of the memories' MRR's in parallel, allowing faster system bring up.