Automatic generation of network function accelerators using component-based synthesis

Pereira, Francisco; Matos, Gonçalo; Sadok, Hugo; Kim, Daehyeok; Martins, Ruben; Sherry, Justine; Ramos, Fernando M. V.; Pedrosa, Luis

doi:10.1145/3563647.3563656

Cited by 3 publications

(2 citation statements)

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“…The software compiler then separates the code and provide binaries that can either be executed in general purposed CPUs or networking devices. The authors in 10 present a framework based on component‐based synthesis that analyses software and generates target specific code (considering either PISA or x86 architectures), tuned according to desired performance (e.g., throughput or resource utilization). This is accomplished by performing an exhaustive symbolic execution to build a complete representation of a network function functionality, resulting in a tree that represents all possible code paths.…”

Section: Challengesmentioning

confidence: 99%

In‐network computing—challenges and opportunities

Silva,

Corujo,

Quevedo

et al. 2023

Internet Technology Letters

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The rapid growth of new applications with high resource demands leads to the need for more computing power. Datacenter servers may not be the most efficient way to run the necessary software. The introduction of programmable dataplanes opens up the possibility to run software directly in the dataplane with lower latency and higher energy efficiency than general purpose servers. Thus, the concept of in‐network computing is introduced. This paper addresses the challenges associated with executing software resorting to programmable networking devices while presenting a high level conceptual architecture including three layers of computing. The paper ends by taking the evaluated challenges into consideration and proposing future research directions for the evolution of the in‐network computing technology.

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Section: Challengesmentioning

confidence: 99%

In‐network computing—challenges and opportunities

Silva,

Corujo,

Quevedo

et al. 2023

Internet Technology Letters

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“…Better compilers for accelerators: To eliminate the effort of porting code across accelerators, researchers have proposed several compilers that automatically generate code that runs on different accelerators [12,46,53,57]. We see such compilers as being complementary to interfaces because they are only useful once the developer has both an implementation and access to the accelerator, and cannot answer questions during the system design stage.…”

Section: Related Workmentioning

confidence: 99%

The Case for Performance Interfaces for Hardware Accelerators

Iyer

Argyraki

et al. 2023

Proceedings of the 19th Workshop on Hot Topics in Operating Systems

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While systems designers are increasingly turning to hardware accelerators for performance gains, realizing these gains is painstaking and error-prone. It can take several person-months to determine if a given accelerator is a good fit for a given piece of code, and accelerators that cost millions of dollars to build can slow down the very systems they were designed to accelerate.We argue that hardware accelerators must come with performance interfaces-interfaces that provide usable information about the accelerator's performance behavior just like semantic interfaces do for functionality-to facilitate their correct use. Since accelerators do not provide new functionality and are only useful if they improve system performance, performance interfaces are as integral to their correct use as semantic interfaces.

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