Automatic generation of transaction level models for rapid design space exploration

Shin, Dongwan; Gerstlauer, Andreas; Peng, Junyu; Dömer, Rainer; Gajski, Daniel D.

doi:10.1145/1176254.1176272

Cited by 21 publications

(8 citation statements)

References 13 publications

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“…In almost all cases, complete system implementations are composed out of a fixed library of communication components, often limited to a single, canonical target architecture template that is proprietary and custom-designed [22] or based on an industry standard [14,17]. Solely targeting design space exploration, several approaches support the automatic generation of TLMs for early prototyping and validation, but without the capability to generate actual implementations [20,1,19].…”

Section: Related Workmentioning

confidence: 99%

Synthesis of optimized hardware transactors from abstract communication specifications

Lee

Park

Gerstlauer

2012

Proceedings of the Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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Increasing system complexity and heterogeneity make system integration and communication synthesis a growing concern. Even with transaction-level modeling and high-level synthesis of hardware, communication interfaces still have to be manually designed at a low protocol level. To address this challenge, we present a design flow for automatic synthesis of hardware transactors, which realize abstractly specified communication semantics on top of protocol-level transactions. Transactor synthesis is tightly coupled with high-level synthesis of computation for integrated computation/communication co-design of complete hardware processors, thus establishing a seamless path from abstract system specifications down to hardware implementations in synthesizable RTL. The flow supports a generic set of communication semantics and target implementations, where transactors are custom-generated for a specific application and architecture combination. Furthermore, we develop protocol stack optimizations that reduce the area and performance overhead of synthesized communication interfaces. We have applied our synthesis flow to several industrial-strength examples under various communication settings. Results show that synthesized interfaces are comparable to manual designs in terms of area and latency, where protocol stack optimizations can reduce area and latency overhead by up to 77% and 21%, respectively.

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Section: Related Workmentioning

confidence: 99%

Synthesis of optimized hardware transactors from abstract communication specifications

Lee

Park

Gerstlauer

2012

Proceedings of the Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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“…This concept is close to our HPC approach, but the examples in [3] are limited to low-level FIFO communication and the authors do not present a solution to automated transactor generation. An approach for the automatic generation of transactors from an abstract input description is presented in [14]. In contrast to our approach, here communication must be modeled using a predefined semantic based on message passing, shared memory accesses and events.…”

Section: Related Workmentioning

confidence: 99%

Embedded software development on top of transaction-level models

Klingauf

Günzel

Schröder

2007

Proceedings of the 5th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis

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Early embedded SW development with transaction-level models has been broadly promoted to improve SoC design productivity. But the proposed APIs only provide low-level read/write operations via a TLM interconnect. SW developers have to implement platform-specific communication procedures and handshake protocols to access HW functions, which requires a deep understanding of both the HW interfaces and the TLM fabric used. In this paper, we propose our concept of hardware procedure calls (HPC) with which HW services are provided to SW processes as remote methods on top of transaction-level communication. To this end, a lightweight HPC protocol is presented, and we propose a method to generate the infrastructure for HPC communication from a straightforward input description. Our experiments show that with HPC, embedded SW development is considerably made easier, and that also the effort to create the transaction-level model itself is reduced.

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“…These approaches do not address transaction level platform modeling without the need to use another language. The closest work is in SpecC TLM generation for design space exploration [14], which still requires designers to understand complex channel modeling in a non-standard SpecC language. One important difference is that their modeling abstraction requires implementation decisions for synchronization to be already made.…”

Section: Related Workmentioning

confidence: 99%