Automatic generation of transducer models for multicore system design

Abstract

This paper presents methods for automatic generation of synthesizable models of Transducer, a highly flexible communication module for interfacing multicore system components. We describe the transducer architecture, comprising the bus interface, high-level communication controllers and buffer management blocks. The well defined architecture and model semantics of the transducer enable its automatic generation. Moreover, the simple interface of the transducer provides for a well defined software interface, making it easy to update the software after changes in multicore system architecture. Our experimental results show that in multicore system design for large applications such as MP3 decoder and JPEG encoder, automatic transducer generation provides productivity gains of 9-23X due to significant savings in communication model development. On the quality axis, we show that multicore communication design using automatically generated transducers has only a 9% overhead in communication delay over a fullyconnected point-to-point communication architecture.

The strange pair: IP-XACT and univerCM to integrate heterogeneous embedded systems

“…Similarly, [5] allows device driver generation provided a target architecture configuration and the partitioning of the EFSM representing the device communication protocol into a set of functionalities. Finally, [8] requires only the target platform configuration to gain automatic generation of transducers.…”