Automatic saboteur placement for emulation-based multi-bit fault injection

Grinschgl, Johannes; Krieg, Armin; Steger, Christian; Weiß, Reinhold; Bock, Holger; Haid, Josef

doi:10.1109/recosoc.2011.5981521

Cited by 12 publications

(5 citation statements)

References 25 publications

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“…The same applies to the work of Mogollon et al [11]. The resource count on LUTs and FFs of FIJI and the work described by Grinschgl et al [17] is similar to FIJI but; however, a hard-core CPU plus additional Block RAM (to implement the CPU's memories) is needed by [17]. For the bitstream-related approaches [9,13,14], a dedicated Altera/Xilinx IP core is required for fault injection that consumes a relatively high number of resources, especially when only a few nets need to be instrumented (5000 LUTs/5400 FFs for Altera's Fault Injection Debugger IP Core, resp.…”

Section: Comparison With Crashtestmentioning

confidence: 87%

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FIJI: Fault InJection Instrumenter

et al. 2019

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FPGAs are increasingly used in safety-critical applications (e.g., in aerospace and automotive engineering). Safety standards stipulate that implemented countermeasures against run-time faults such as detection and isolation of affected components, automatic reconfiguration, and redundancy mechanisms must be adequately verified. To that end, fault injection tests by various means have been established as a suitable method. For such tests, faults can be provoked by radiation, simulation, or manipulating the design, for example, by inserting additional logic or manipulating the synthesis flow. This work briefly summarizes the various fault injection approaches with a focus on methods that are capable of stressing critical nets of a design running on actual hardware without requiring to re-synthesize. While the state-of-the-art tools can work with complex designs, they often lack controllability of the exact timing of the injection events (which is important to track the system's response on faults in a logic simulation) and/or use a high amount of FPGA resources. To overcome these issues, we propose a resource-saving netlist-based fault injection framework Fault InJection Instrumenter (FIJI) that can target individual nets at test runtime. This paper presents FIJI's work flow, implementation details, and an evaluation in terms of FPGA resources, timing impact, and performance during instrumentation and test execution. The FIJI framework has been made publicly available by the authors under an open-source license.

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Section: Comparison With Crashtestmentioning

confidence: 87%

“…Approaches that modify the DUT's HDL representation are performed by Baraza et al [16], Grinschgl et al [17], and Jeitler, Delvai, and Reichör (FuSE) [18]. Baraza…”

Section: Hdl-level Approachesmentioning

confidence: 99%

FIJI: Fault InJection Instrumenter

et al. 2019

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“…Similarly, in [21], authors have presented different functions of saboteur (such as bit flip, bidirectional, n-bit saboteur etc). The complex scenarios of fault injection can also be implemented using a saboteur by integrating different components such as gates and flip-flops [22].…”

Section: A Related Workmentioning

confidence: 99%

EFIC-ME: A Fast Emulation Based Fault Injection Control and Monitoring Enhancement

Abideen

Rashid

2020

IEEE Access

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The security and dependability of embedded systems are increasing due to the sensitive and condensed structure of nanodevices. As the chip area shrinks and the technologies upgrade, the probability of Single Event Upset or Multi Bit Upset proliferate which may lead to unexpected results. This article presents a fault-injection tool called EFIC-ME (Emulation based Fault Injection Control and Monitoring Enhancement) using an emulation technique with a reasonable contribution to flexibility and controllability. Existing emulation based fault-injection tools, targeting Field Programmable Gate Arrays (FPGA), reveal high efficiency and low emulation time, but they still lack the control of fault injection time. The proposed tool (EFIC-ME) achieves a low emulation time and provides a sophisticated way to inject the fault in a specific location at a specific clock cycle inside the Design Under Test (DUT). Additionally, it also employs an observability mechanism to monitor the current state of flip-flops on a user defined time. In the context of high emulation speed, it provides an Opal Kelly FPGA interface between the host controller and emulator. In order to evaluate the dependability of the proposed tool, a mechanism has been provided in terms of FoEA (Factors of emulation analysis) and fault injection rate. The FoEA estimates the failure probability of a complete DUT and the failure probability of a specific location inside the DUT which directly affects an output. The designed architecture is initially validated using simulation to verify the functional characteristics. Subsequently, the fault injection campaign has been performed on Kintex-7 FPGA for seven different DUTs. The achieved results have been discussed and compared with state-of-the-art in terms of various performance attributes.INDEX TERMS Dependability, emulation, embedded systems, fault injection, hardware security, Opal Kelly field programmable gate array (FPGA), flexibility.

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“…As the main goal of this chapter is to assess the degree of acceleration achieved by the proposed framework in the faultinjection phase, FIUs are inserted manually into the net list of our design. However, all FIUs can be automatically inserted using the well-known automatic saboteur insertion techniques [Gri11].…”

Section: Fault-injection Unitsmentioning

confidence: 99%

“…During the set-up phase, the user incorporates FIUs into the HDL representation of the system. As mentioned before, this step can be carried out automatically [Gri11]. The FIU incorporation is a partial code-modification that imports FIUs into the predefined nets/registers inside the HDL net list.…”

Section: Embedding Fius In the Fault-injection Phasementioning

confidence: 99%

Modelling and mitigation of soft-errors in CMOS processors

Rohani¹

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Automatic saboteur placement for emulation-based multi-bit fault injection

Cited by 12 publications

References 25 publications

FIJI: Fault InJection Instrumenter

FIJI: Fault InJection Instrumenter

EFIC-ME: A Fast Emulation Based Fault Injection Control and Monitoring Enhancement

Modelling and mitigation of soft-errors in CMOS processors

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