Automatic SIMD Vectorization of SSA-based Control Flow Graphs

Karrenberg, Ralf

doi:10.1007/978-3-658-10113-8

Cited by 14 publications

(10 citation statements)

References 63 publications

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“…Post-Dominator Reconvergence. A large body of earlier work assumes that diverged threads will not reconverge before the immediate post-dominator (IPD) [Coutinho et al 2011;Farrell and Kieronska 1996;Habermaier and Knapp 2012;Karrenberg 2015]. IPD reconvergence became popular through its adoption in NVIDIA GPUs starting with Tesla [Lindholm et al 2008].…”

Section: Related Workmentioning

confidence: 99%

An abstract interpretation for SPMD divergence on reducible control flow graphs

Rosemann

Moll

Hack

2021

Proc. ACM Program. Lang.

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Vectorizing compilers employ divergence analysis to detect at which program point a specific variable is uniform, i.e. has the same value on all SPMD threads that execute this program point. They exploit uniformity to retain branching to counter branch divergence and defer computations to scalar processor units. Divergence is a hyper-property and is closely related to non-interference and binding time. There exist several divergence, binding time, and non-interference analyses already but they either sacrifice precision or make significant restrictions to the syntactical structure of the program in order to achieve soundness. In this paper, we present the first abstract interpretation for uniformity that is general enough to be applicable to reducible CFGs and, at the same time, more precise than other analyses that achieve at least the same generality. Our analysis comes with a correctness proof that is to a large part mechanized in Coq. Our experimental evaluation shows that the compile time and the precision of our analysis is on par with LLVM's default divergence analysis that is only sound on more restricted CFGs. At the same time, our analysis is faster and achieves better precision than a state-of-the-art non-interference analysis that is sound and at least as general as our analysis.

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Section: Related Workmentioning

confidence: 99%

An abstract interpretation for SPMD divergence on reducible control flow graphs

Rosemann

Moll

Hack

2021

Proc. ACM Program. Lang.

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“…Reference [45] detects computations in a program that may be performed simultaneously in SIMD lanes and optimizes for vector register usage to minimize memory traffic. The Region Vectorizer [28] is the first open source vectorizer that works on the whole-function level. After converting a whole function to an SSA-based representation, execution flows are traced, masks generated, and loops reordered.…”

Section: Related Workmentioning

confidence: 99%

Flynn’s Reconciliation

Thuerck

Weber²,

Bifulco³

2021

ACM Trans. Archit. Code Optim.

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A large portion of the recent performance increase in the High Performance Computing (HPC) and Machine Learning (ML) domains is fueled by accelerator cards. Many popular ML frameworks support accelerators by organizing computations as a computational graph over a set of highly optimized, batched general-purpose kernels. While this approach simplifies the kernels’ implementation for each individual accelerator, the increasing heterogeneity among accelerator architectures for HPC complicates the creation of portable and extensible libraries of such kernels. Therefore, using a generalization of the CUDA community’s warp register cache programming idiom, we propose a new programming idiom (CoRe) and a virtual architecture model (PIRCH), abstracting over SIMD and SIMT paradigms. We define and automate the mapping process from a single source to PIRCH’s intermediate representation and develop backends that issue code for three different architectures: Intel AVX512, NVIDIA GPUs, and NEC SX-Aurora. Code generated by our source-to-source compiler for batched kernels, borG, competes favorably with vendor-tuned libraries and is up to 2× faster than hand-tuned kernels across architectures.

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“…Earlier work [Eichenberger et al 2004;Nuzman et al 2006;Ren et al 2006;Sreraman and Govindarajan 2000] applied strip mining to exploit parallelism across consecutive loop iterations by adopting the technology developed for vector machines [Zima and Chapman 1991]. Over the years, several problems have been addressed, including non-unit array accesses [Nuzman et al 2006], nonunified data alignment [Eichenberger et al 2004;Larsen et al 2002], virtual vectors [Wu et al 2005], polyhedral transformations [Kong et al 2013;Trifunovic et al 2009], branch divergence [Shin 2007;Sujon et al 2013], function calls [Karrenberg and Hack 2011;Karrenberg 2015], and split vectorization [Nuzman et al 2011]. Loop-level vectorization works well for loops with regular computations that exhibit little dependences but often poorly for loops with loop-carried dependences (caused by IAA and ICF in Table II), as evaluated here.…”

Section: Related Workmentioning

confidence: 99%

A Compiler Approach for Exploiting Partial SIMD Parallelism

Zhou

Xue

2016

ACM Trans. Archit. Code Optim.

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Existing vectorization techniques are ineffective for loops that exhibit little loop-level parallelism but some limited superword-level parallelism (SLP). We show that effectively vectorizing such loops requires partial vector operations to be executed correctly and efficiently, where the degree of partial SIMD parallelism is smaller than the SIMD datapath width. We present a simple yet effective SLP compiler technique called PAVER (PArtial VEctorizeR), formulated and implemented in LLVM as a generalization of the traditional SLP algorithm, to optimize such partially vectorizable loops. The key idea is to maximize SIMD utilization by widening vector instructions used while minimizing the overheads caused by memory access, packing/ unpacking, and/or masking operations, without introducing new memory errors or new numeric exceptions. For a set of 9 C/C++/Fortran applications with partial SIMD parallelism, PAVER achieves significantly better kernel and whole-program speedups than LLVM on both Intel's AVX and ARM's NEON.

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Automatic SIMD Vectorization of SSA-based Control Flow Graphs

Cited by 14 publications

References 63 publications

An abstract interpretation for SPMD divergence on reducible control flow graphs

An abstract interpretation for SPMD divergence on reducible control flow graphs

Flynn’s Reconciliation

A Compiler Approach for Exploiting Partial SIMD Parallelism

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