Automatic Synthesis of Compressor Trees: Reevaluating Large Counters

Abstract

Despite the progress of the last decades in electronic design automation, arithmetic circuits have always received way less attention than other classes of digital circuits. Logic synthesisers, which play a fundamental role in design today, play a minor role on most arithmetic circuits, performing some local optimisations but hardly improving the overall structure of arithmetic components. Architectural optimisations have been often studied manually, and only in the case of very common building blocks such as fast adders and multi-input adders, ad-hoc techniques have been developed. A notable case is multi-input addition, which is the core of many circuits such as multipliers, etc. The most common technique to implement multi-input addition is using compressor trees, which are often composed of carry-save adders (based on (3 : 2) counters, i.e., full adders). A large body of literature exists to implement compressor trees using large counters. However, all the large counters were built by using full and half adders recursively. In this paper we give some definite answers to issues related to the use of large counters. We present a general technique to implement large counters whose performance is much better than the ones composed of full and half adders. Also we show that it is not always useful to use larger optimised counters and sometimes a combination of various size counters gives the best performance. Our results show 15% improvement in the critical path delay. In some cases even hardware area is reduced by using our counters.

An FPGA Logic Cell and Carry Chain Configurable as a 6:2 or 7:2 Compressor

“…Wallace and Dadda trees are two specific compressor tree architectures; many others have also been proposed [Swartzlander 1973;Stenzel et al 1977;Weinberger 1981;Santoro and Horowitz 1988;Song and De Micheli 1991;Fadavi-Arkedani 1993;Stelling and Oklobdzija 1996;Stelling et al 1998;Kwon et al 2002;Um and Kim 2002;Mora Mora et al 2006;Verma and Ienne 2007a].…”

“…The key is not to use trees of traditional carry-propagate adders, that is, circuits that produce the sum of two (signed) binary integers; instead, the integers are aggregated together using a circuit called a compressor tree. Numerous methods for compressor tree generation have been published since their introduction in the early 1960s [Wallace 1964;Dadda 1965;Swartzlander 1973;Stenzel et al 1977;Weinberger 1981;Santoro and Horowitz 1988;Song and De Micheli 1991;Fadavi-Arkedani 1993;Oklobdzija and Villeger 1995;Stelling and Oklobdzija 1996;Stelling et al 1998;Kwon et al 2002;Um and Kim 2002;Mora Mora et al 2006;Verma and Ienne 2007a], mostly in the context of parallel multiplication; more generally, these circuits can also sum k > 2 integers.…”

A novel FPGA logic block for improved arithmetic performance

“…Verma and Ienne [35] developed an integer linear program (ILP) that could optimally synthesize compressor trees from a library of m:n counters. To bound the runtime of the synthesis procedure, they limited m to the range [1,8].…”

Improving synthesis of compressor trees on FPGAs via integer linear programming

“…Verma and Ienne [10] used an ILP to construct a compressor tree using a set of counters ranging from 2-8 input bits. This method is similar to ours in its use of larger counters.…”

“…One of the most important arithmetic operations in many DSP and video processing applications is multi-operand addition, i.e., the addition of k > 2 binary integers. Multi-input addition occurs in the context of FIR filters [1], correlation of 3G wireless base-station channel cards [2], motion estimation in video coding [3], and partial product summation in parallel multiplication [4,5,6,7,[8][9][10]11]. Verma and Ienne [12] developed a set of circuit transformations that can expose large compressor trees from disparate addition and multiplication operations.…”