Automatic synthesis of customized local memories for multicluster application accelerators

Abstract

Distributed local memories, or scratchpads, have been shown to effectively reduce cost and power consumption of application-specific accelerators while maintaining performance. The design of the local memory organization must take several factors into account, including the memory bandwidth and size requirements of the program and the distribution of program data among the memories. In addition, when register structures and function units in the accelerator are clustered, the effects of intercluster communication should be taken into account. This work proposes a technique to synthesize the local memory architecture of a clustered accelerator using a phase-ordered approach. First, the dataflow graph is pre-partitioned to define a performance-centric grouping of the operations. Second, memory synthesis is performed by combining multiple data structures into a set of physical memories that minimizes cost while maintaining a performance threshold. Finally, post-partitioning is performed to determine the final assignment of operations to clusters given the memory organization. Results show that customization reduces memory cost from 2% to 59% over a naïve scheme that utilizes one physical memory per program data structure. Further, pre-partitioning is shown to reduce the intercluster communication required to achieve a fixed performance.

Storage assignment during high-level synthesis for configurable architectures

“…Panda et al [4] investigated architectural-level exploration techniques for embedded processors with complicate hierarchical memory systems. Based on the PICO method, Kurdur et al [5] presented an ILP formulation to solve the storage arrangement problem. Early efforts on utilizing multiple memory modules on FPGA [6] allocated an entire array to a single memory module rather than partitioning data arrays.…”