Automatic SystemC Code Generation from UML Models at Early Stages of Systems on Chip Design

Boutekkouk, Fateh

doi:10.5120/1215-1744

Cited by 15 publications

(3 citation statements)

References 11 publications

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“…Most of related works on hardware design using UML as a high level modeling language generate imperative HDL codes at the system level. In [1], the authors pro-posed an approach for automatic generation of SystemC code from UML diagrams at early stage of SoCs (Systems on Chip) designs, using two levels of abstraction: In the first level, they use UML sequence diagrams to generate the SystemC code which is dedicated to algorithmic space exploration and simulation. In the second level, they implement the messages occurring in sequence diagrams using UML activity diagrams where actions are expressed in the C++ Action Language (AL).…”

Section: Related Workmentioning

confidence: 99%

“…To this aim, researchers have created UML profiles such as UML-SystemC [2], UML-SoC [18], MARTE [8], or SysML [3] that extend UML with the appropriate constructs to hierarchically describe complex hardware designs and analyze their properties. Thereafter, they have created approaches to generate a system level implementation through imperative intermediate HDL code such as VHDL [3,5], Verilog [5,7] or SystemC [1,2,5,6], to bridging the gap between UML high level description and the micro-architecture level description.…”

Section: Introductionmentioning

confidence: 99%

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A SysML and CLEAN-based methodology for digital circuits design

Lakhdara¹,

Merniz²

2016

IJHPSA

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Due to the ever complexity of digital systems, there is a noticeable need for more abstract and structural mechanisms as well as design methodologies that systematically and formally derive low level concrete designs from high level abstract ones. To this aim, we present a methodological design approach that automatically generates a functional HDL code from SysML diagrams modeling hardware designs. The generated HDL code is both reliable and executable. While the first feature remains crucial for low level design refinements, the second one enables evaluating design performances at early stages. A case study involving the functional implementation of an ALU (Arithmetic Logic Unit) through Clean code generated from high level SysML diagrams is given, to practically show the potential features of the proposed approach.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A SysML and CLEAN-based methodology for digital circuits design

Lakhdara¹,

Merniz²

2016

IJHPSA

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“…Previous research studies that focused on hardware design using UML as a modelling language generate imperative HDL codes at the system level. In (Boutekkouk, 2010), the authors proposed an approach for the automatic generation of SystemC code from UML diagrams at an early stage of System on Chip (SoC) design, using two levels of abstraction. At the first level, they use UML sequence diagrams to generate the SystemC code that is dedicated to algorithmic space exploration and simulation.…”

Section: Related Workmentioning

confidence: 99%

A SysML and CLEAN Based Methodology for RISC Processor Micro-Architecture Design

Lakhdara¹,

Merniz

2015

International Journal of Embedded and Real-Time Communication Systems

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Nowadays, processor micro-architectures are becoming more and more complex. Consequently, designers increasingly need powerful abstraction and structuration mechanisms, as well as design methodologies that automatically and formally derive low-level concrete designs from high-level abstract ones. In this context, this paper proposes a methodology for RISC processor micro-architecture design. The proposed methodology uses mainly SysML to model both ISA and MA levels and the functional language CLEAN to describe them. Functional specifications in CLEAN are automatically generated from the ISA and MA models. These specifications, which are executable and formally verifiable, are used for simulation and verification. The proposed approach is validated by a case study that consists of designing the micro-architecture of MIPS processor. It shows how to easily model and generate CLEAN specifications describing the ISA and MA levels. It also illustrates, with multiple cases, how the generated specifications are used to simulate the MA. The results of the simulation phase prove the efficiency of the proposed modeling and code generation techniques.

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