Automatic Test Generation From Semi-formal Specifications for Functional Verification of System-on-Chip Designs

Kirchsteiger, Christoph M.; Grinschgl, Johannes; Trummer, Christoph; Steger, Christian; Weiß, Reinhold; Pistauer, Markus

doi:10.1109/systems.2008.4519044

Cited by 18 publications

(12 citation statements)

References 8 publications

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“…We have implemented our methodology in the HW/SW co-design tool SyAD R (System Architect Designer) [9], [11] to demonstrate it. SyAD R provides the development of entire HW/SW system models and supports a multilanguage and multi-level co-simulation framework of Sys-temC, MATLAB Simulink, VHDL and VHDL-AMS.…”

Section: Resultsmentioning

confidence: 99%

Rapid exploration of multimedia system-on-chips with automatically generated software performance models

Kirchsteiger

Schweitzer

Trummer

et al. 2008

2008 IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia

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A challenge in the design space exploration of todays' multimedia system-on-chip (SoC) designs is to rapidly evaluate the large number of different processor types. This limitation is resolved by our methodology, originated from the SIMBA 1 project. It automatically generates a Sys-temC performance model of the software code with respect to the chosen processor type. The generated performance model consists of the original software C-code annotated with SystemC wait statements to consider the execution time on the target processor. These wait statements are automatically determined by the target cross-compiler's assembler code and the processor datasheet and consider also memory accesses and pipeline effects. In our experiments we automatically generate both a performance model of an ARM and a TI processor. This only requires the target cross-compiler and the processor datasheet and is widely applicable to various processor types. We show that our models can be used easily to compare the software performance on these platforms. We also demonstrate that the models can be smoothly integrated into an existing multimedia SoC for a rapid software-driven architecture exploration.978-1-4244-2612-6/08/$25.00

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Section: Resultsmentioning

confidence: 99%

Rapid exploration of multimedia system-on-chips with automatically generated software performance models

Kirchsteiger

Schweitzer

Trummer

et al. 2008

2008 IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia

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“…These languages are parsed and converted into UML [19,20] or temporal logic languages [21,22] to guide vector sequence generation. These semiformal specifications are easy to use, but they are ambiguous and incapable of specifying all types of functional operations.…”

Section: Related Workmentioning

confidence: 99%

Simulation-Based Hardware Verification with a Graph-Based Specification

Chen

Wang

2018

Mathematical Problems in Engineering

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Simulation-based verification continues to be the primary technique for hardware verification due to its scalability and ease of use; however, it lacks exhaustiveness. Although formal verification techniques can exhaustively prove functional correctness, they are limited in terms of the scale of their design due to the state-explosion problem. Alternatively, semiformal approaches can involve a compromise between scalability, exhaustiveness, and resource costs. Therefore, we propose an event-driven flow graph-based specification, which can describe the cycle-accurate functional behaviors without the exploration of whole state space. To efficiently generate input sequences according to the proposed specification, we introduce a functional automatic test pattern generation (ATPG) approach, which involves the proposed intelligent redundancy-reduction strategy to solve problems of random test vectors. We also proposed functional coverage criterion based on the formal specification to support a more reliable measure of verification. We implement a verification platform based on the proposed semiformal approach and compare the proposed semiformal approach with the constrained randomized test (CRT) approach. The experiment results show that the proposed semiformal verification method ensures a more exhaustive and effective exploration of the functional correctness of designs under verification (DUVs).

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“…Each component contains metadata and use cases describing its functionality. The use cases are specified in a semi-formal format (Kirchsteiger et al, 2008). Component selection is performed in two steps.…”

Section: Component Selection Strategymentioning

confidence: 99%

“…Each field is com- to the matching components in the library and ranked in a fuzzy or strict way to reduce the search space. A different algorithm is utilized for the semi-formal use cases (see Kirchsteiger et al, 2008) which contain natural text structured into several sections. Similarity analysis takes advantage of the informal sentence structure of the use cases and calculates a similarity score for each IP component.…”

Section: Ip Selectionmentioning

confidence: 99%

An IP-XACT Library extended with verification information for functionality-based component selection

Ruggenthaler

Trummer

Steger

et al. 2010

Elektrotech. Inftech.

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In the Electronic Design and Automation (EDA) industry a gap between design and productivity exists and is even expanding. Also, consumers demand fancy products and new features at a faster pace. Consequently, to fulfill these rigid design cycles companies are reusing Intellectual Property (IP) components provided by third-party suppliers instead of creating them anew. However, no common format exists amongst companies which complicates IP exchange and reuse. Moreover, verification information, if existing, is provided separate from the IP. This paper introduces a novel approach to enable IP exchange with added verification information and metadata. To represent IP the new IP-XACT format is extended. Our developed library is able to store the extended IP with all its resources. The novel component selection strategy uses this information to retrieve matching IP based on their functionality and achieves accurate results. ß Springer-Verlag 2009

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Automatic Test Generation From Semi-formal Specifications for Functional Verification of System-on-Chip Designs

Cited by 18 publications

References 8 publications

Rapid exploration of multimedia system-on-chips with automatically generated software performance models

Rapid exploration of multimedia system-on-chips with automatically generated software performance models

Simulation-Based Hardware Verification with a Graph-Based Specification

An IP-XACT Library extended with verification information for functionality-based component selection

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