Automatic TLM Fault Localization for SystemC

Le, Hoang M.; Große, Daniel; Drechsler, Rolf

doi:10.1109/tcad.2012.2188800

Cited by 25 publications

(2 citation statements)

References 21 publications

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“…Griesmayer's approach has also been applied to hardware designs in SystemC [40], often combined with different solver technologies such as QBF [62] or unsatisfiable cores [64]. Our results indicate that "plain old SAT/SMT" is still sufficient, but these technologies could be considered as alternatives in our approach as well.…”

Section: Fault Localisationmentioning

confidence: 90%

Fast test suite-driven model-based fault localisation with application to pinpointing defects in student programs

2017

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Fault localisation, i.e. the identification of program locations that cause errors, takes significant effort and cost. We describe a fast model-based fault localisation algorithm that, given a test suite, uses symbolic execution methods to fully automatically identify a small subset of program locations where genuine program repairs exist. Our algorithm iterates over failing test cases and collects locations where an assignment change can repair exhibited faulty behaviour. Our main contribution is an improved search through the test suite, reducing the effort for the symbolic execution of the models and leading to speed-ups of more than two orders of magnitude over the previously published implementation by Griesmayer et al. We implemented our algorithm for C programs, using the KLEE symbolic execution engine, and demonstrate its effectiveness on the Siemens TCAS variants. Its performance is in line with recent alternative model-based fault localisation techniques, but narrows the location set further without rejecting any genuine repair locations where faults can be fixed by changing a single assignment. We also show how our tool can be used in an educational context to improve self-guided learning and accelerate assessment. We apply our algorithm to a large selection of actual student coursework submissions, providCommunicated by Prof. Alfonso Pierantonio, Jasmin Blanchette, Francis Bordeleau, Nikolai Kosmatov, Gabi Taentzer, and Manuel Wimmer. We show this using small test suites, already provided in the coursework management system, and on expanded test suites, demonstrating the scalability of our approach. We also show compliance with test suites does not reliably grade a class of "almost-correct" submissions, which our tool highlights, as being close to the correct answer. Finally, we show an extension to our tool that extends our fast localisation results to a selection of student submissions that contain two faults.

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Section: Fault Localisationmentioning

confidence: 90%

Fast test suite-driven model-based fault localisation with application to pinpointing defects in student programs

2017

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“…The approach involves a comprehensive set of mutation operators for concurrency constructs in SystemC and defines a concurrent coverage metric considering multiple execution schedules that a concurrent program can generate. [24] introduces an automatic fault localization approach for TLM designs based on bounded model checking. Faults and possible fixes are first formalized in a fault model.…”

Section: Related Workmentioning

confidence: 99%

Testbench Qualification of SystemC TLM Protocols through Mutation Analysis

Bombieri

Fummi

Guarnieri

et al. 2014

IEEE Trans. Comput.

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Transaction-level modeling (TLM) has become the de-facto reference modeling style for system-level design and verification of embedded systems. It allows designers to implement high-level communication protocols for simulations up to faster than at register-transfer level (RTL). To guarantee interoperability between TLM IP suppliers and users, designers implement the TLM communication protocols by relying on a reference standard, such as the standard OSCI for SystemC TLM. Functional correctness of such protocols as well as their compliance to the reference TLM standard are usually verified through user-defined testbenches, whose high quality and completeness play a key role for an efficient TLM design and verification flow. This article presents a methodology to apply mutation analysis, a technique applied in literature for SW testing, for measuring the testbench quality in verifying TLM protocols. In particular, the methodology aims at (i) qualifying the testbenches by considering both the TLM protocol correctness and their compliance to a defined standard (i.e., OSCI TLM), (ii) optimizing the simulation time during mutation analysis by avoiding mutation redundancies, and (iii) driving the designers in the testbench improvement. Experimental results on benchmarks of different complexity and architectural characteristics are reported to analyze the methodology applicability.

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