Automatic topology-based identification of instruction-set extensions for embedded processors

Pozzi, L.; Vuletic, M.; Ienne, P.

doi:10.1109/date.2002.998496

Cited by 12 publications

(22 citation statements)

References 1 publication

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“…However, these restrictions can sometime lead to very efficient enumeration algorithms. For example, Pozzi et al [19] have developed a linear time algorithm to identify the maximal Multiple Inputs Single Output (MISO) patterns. J. Cong et al [11] enumerate all possible K-feasible MISO patterns (where K is the input operands constraint) through a single pass of the DFG.…”

Section: Related Workmentioning

confidence: 99%

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Disjoint Pattern Enumeration for Custom Instructions Identification

Mitra

2007

2007 International Conference on Field Programmable Logic and Applications

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Extensible processors allow addition of application-specific custom instructions to the core instruction set architecture. These custom instructions are selected through an analysis of the program's dataflow graphs. The characteristics of certain applications and the modern compiler optimization techniques (e.g., loop unrolling, region formation, etc.) have lead to substantially larger dataflow graphs. Hence, it is computationally expensive to automatically select the optimal set of custom instructions. Heuristic techniques are often employed to quickly search the design space. In order to leverage full potential of custom instructions, our previous work proposed an efficient algorithm for exact enumeration of all possible candidate instructions (or patterns) given the dataflow graphs. But the algorithm was restricted to connected computation patterns. In this paper, we describe an efficient algorithm to generate all feasible disjoint patterns starting with the set of feasible connected patterns. Compared to the state-of-the-art technique, our algorithm achieves orders of magnitude speedup while generating the identical set of candidate disjoint patterns.

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Section: Related Workmentioning

confidence: 99%

“…Previous approaches either put very limiting constraints on the number of operands [11,19] or use heuristics [7,10] to explore the design space quickly. However, it has been shown [6,22] that such approaches can significantly restrict the performance potential of using custom instructions.…”

Section: Introductionmentioning

confidence: 99%

Disjoint Pattern Enumeration for Custom Instructions Identification

Mitra

2007

2007 International Conference on Field Programmable Logic and Applications

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“…An other problem is given by the management of disconnected graphs. Even though the study of the problem including disconnected graphs in the analysis allows for exploiting the parallelism provided by considering each connected components at the same time [40,12,14], in many cases the authors have taken up only the study of connected graphs [10,28,25,31,32,41], shifting the study of disconnected graph in the study of k graphs, where k is the number of connected components.…”

Section: Instruction Generationmentioning

confidence: 99%

“…For the first one, a representative example is introduced in [58,28] which addresses the generation of MISO instructions of maximal size, called MAXMISO. The proposed algorithm exhaustively enumerates all MAXMISOs.…”

Section: The Type Of Instructionsmentioning

confidence: 99%

“…The processor is then manually tailored to include the new capabilities. Although human ingenuity in manual creation of custom capabilities creates high quality results, performance and time-to-market requirements as well as the growing complexity of the design space, can benefit from an automatic design flow for the use of these new capabilities [28,29,12,30,31,32,13,14,60]. Moreover the selection of multiple custom instructions from a large set of candidates involves complex tradeoff and can be difficult to be performed manually.…”

Section: Introduction To the Problemmentioning

confidence: 99%

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The Instruction-Set Extension Problem: A Survey

Galuzzi

Bertels

Lecture Notes in Computer Science

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Abstract.Over the last years, we have witnessed the increased use of Application-Specific Instruction-Set Processors (ASIPs). These ASIPs are processors that have a customizable instruction-set, which can be tuned towards specific requirements. The identification, definition and implementation of those operations that provide the largest performance improvement and that should be hardwired, extending in this way the Instruction-Set, constitutes a major challenge. The purpose of this paper is to investigate and study the issues regarding the customization of an Instruction-Set in function of the specific requirements of an application. Additionally, the paper provides an overview of all relevant aspects of the problem and compensates the lack of a general view of the problem in the existing literature.

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A retargetable framework for compiler/architecture co-development

Scharwaechter

Kammler

Leupers

et al. 2011

Des Autom Embed Syst

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Compiler-in-the-Loop (CiL) architecture exploration is widely accepted as being the right track for fast development of Application Specific Instruction-set Processors (ASIP). In this context, both, automatic application-specific Instruction Set Extension (ISE) and code generation by a compiler have received huge attention in the past. Together, both techniques enable processor designers to quickly adapt a processor's Instruction Set Architecture (ISA) to the needs of a certain set of applications and to provide an appropriate high-level programming model. This manuscript presents a tool flow for identification and utilization of Custom Instructions (CIs) during architecture exploration in an automated fashion. By embedding this tool flow in an industry-proven architecture exploration framework, a methodology for simultaneous compiler/architecture co-exploration is derived. The advantage of the presented tool flow lies in its ability to develop a reusable ISA and an appropriate compiler for a set of applications and therefore to support the design of programmable architectures. In addition, ASIP architecture exploration is effectively improved since time consuming application analysis and compiler retargeting is automated. Through compilation and simulation of several benchmarks in accordance to extended ISAs, reliable feedback on speedup, code size and usability of identified CIs is provided. Furthermore, results on area consumption for extended ISAs are presented in order to compare the obtained speedup with the invested hardware effort of new CIs.Extension of Conference Paper: An earlier version [66] of this paper appeared in the proceedings of the 5th IEEE/ACM international conference on hardware/software codesign and system synthesis. It introduces a code-generator named CBurg which is now applied for implementing a code-selector engine of the CoSy compiler system from ACE. Additionally, a methodology for recurrence-aware identification of custom instructions is presented that builds on the data flow graphs from the compiler's intermediate representation. At the same time, it produces a code-generator description which is used to retarget the compiler backend to a new instruction set.

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Automatic topology-based identification of instruction-set extensions for embedded processors

Cited by 12 publications

References 1 publication

Disjoint Pattern Enumeration for Custom Instructions Identification

Disjoint Pattern Enumeration for Custom Instructions Identification

The Instruction-Set Extension Problem: A Survey

A retargetable framework for compiler/architecture co-development

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