Automatically characterizing large scale program behavior

SherwoodTimothy,; PerelmanErez,; Hamerly, Greg; CalderBrad,

doi:10.1145/635506.605403

Cited by 166 publications

(171 citation statements)

References 13 publications

Supporting

Mentioning

170

Contrasting

Unclassified

Order By: Relevance

“…Antoniol et al [20] used text mining to separate bug reports from feature requests. More generally, approaches as presented by Sherwood et al [21] and Bowring et al [22] automatically classify program behavior using execution data. In contrast, the work presented in this paper, uses test step failure patterns to automatically classify whether test failures report code defects or are due to test and infrastructure issues.…”

Section: A Classifying Program Failures and Behaviormentioning

confidence: 99%

Empirically Detecting False Test Alarms Using Association Rules

Herzig

Nagappan

2015

2015 IEEE/ACM 37th IEEE International Conference on Software Engineering

View full text Add to dashboard Cite

Applying code changes to software systems and testing these code changes can be a complex task that involves many different types of software testing strategies, e.g. system and integration tests. However, not all test failures reported during code integration are hinting towards code defects. Testing large systems such as the Microsoft Windows operating system requires complex test infrastructures, which may lead to test failures caused by faulty tests and test infrastructure issues. Such false test alarms are particular annoying as they raise engineer attention and require manual inspection without providing any benefit. The goal of this work is to use empirical data to minimize the number of false test alarms reported during system and integration testing. To achieve this goal, we use association rule learning to identify patterns among failing test steps that are typically for false test alarms and can be used to automatically classify them. A successful classification of false test alarms is particularly valuable for product teams as manual test failure inspection is an expensive and time-consuming process that not only costs engineering time and money but also slows down product development. We evaluating our approach on system and integration tests executed during Windows 8.1 and Microsoft Dynamics AX development. Performing more than 10,000 classifications for each product, our model shows a mean precision between 0.85 and 0.90 predicting between 34% and 48% of all false test alarms.

show abstract

Section: A Classifying Program Failures and Behaviormentioning

confidence: 99%

Empirically Detecting False Test Alarms Using Association Rules

Herzig

Nagappan

2015

2015 IEEE/ACM 37th IEEE International Conference on Software Engineering

View full text Add to dashboard Cite

show abstract

“…However, this approach is limited; while it may allow one to more quickly simulate full workloads, it does not solve the problem of simulating that workload on a detailed model when an architect is negotiating finer details and trade-offs. A more favorable approach to increase analysis throughput is to use SimPoint [4] to distill out the important and often repetitive phases of benchmarks, experiment on those phases, and then project workload performance from that small subset of the workload. This approach allows an architect to simulate effectively full workloads on any type of microarchitecture model, regardless of detail, in a more tractable amount of time.…”

Section: Introductionmentioning

confidence: 99%

A structured approach to the simulation, analysis and characterization of smartphone applications

Sunwoo

Wang

Ghosh

et al. 2013

2013 IEEE International Symposium on Workload Characterization (IISWC)

View full text Add to dashboard Cite

Full-system simulators are invaluable tools for designing new architectures due to their ability to simulate full applications as well as capture operating system behavior, virtual machine or hypervisor behavior, and interference between concurrently-running applications. However, the systems under investigation and applications under test have become increasingly complicated leading to prohibitively long simulation times for a single experiment. This problem is compounded when many permutations of system design parameters and workloads are tested to investigate system sensitivities and full-system effects with confidence.In this paper, we propose a methodology to tractably explore the processor design space and to characterize applications in a full-system simulation environment. We combine SimPoint, Principal Component Analysis and Fractional Factorial experimental designs to substantially reduce the simulation effort needed to characterize and analyze workloads. We also present a noninvasive user-interface automation tool to allow us to study all types of workloads in a simulation environment. While our methodology is generally applicable to many simulators and workloads, we demonstrate the application of our proposed flow on smartphone applications running on the Android operating system within the gem5 simulation environment.

show abstract

“…However we do not expect that the result will differ much. Reference input sets, fast-forwarded to the first Simpoint [21] [22] with cache and branch predictor warm-up, and a detailed run of 200M are used. Detailed runs of 2B cycles after fast-forwarding are used for the IPC impact study.…”

Section: F Relationship To Prior Workmentioning

confidence: 99%

Combating Aging with the Colt Duty Cycle Equalizer

Gunadi

Sinkar

Kim

et al. 2010

2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture

View full text Add to dashboard Cite

Bias temperature instability, hot-carrier injection, and gate-oxide wearout will cause severe lifetime degradation in the performance and the reliability of future CMOS devices. The design guardband to counter these negative effects will be too expensive, largely due to the worst-case behavior induced by the uneven utilization of devices on the chip. To mitigate these effects over a chip's lifetime, this paper proposes Colt, a simple yet holistic scheme to balance the utilization of devices in a processor by equalizing the duty cycle ratio of circuits' internal nodes and the usage frequency of devices. Colt relies on alternating true-and complement-mode operations to equalize the duty cycle ratio of signals (thus the utilization of devices) in most data path and storage devices. Colt also employs a pseudorandom indexing scheme to balance the usage of entries in storage structures that often exhibit highly uneven utilization of entries. Finally, an operand-swapping scheme equalizes utilization of the left and right operand data paths. The proposed mechanisms impose trivial overhead in area, complexity, power, and performance, while recapturing 27% of aging-induced performance degradation and improving mean time to failure by an estimated 40%.

show abstract

Automatically characterizing large scale program behavior

Cited by 166 publications

References 13 publications

Empirically Detecting False Test Alarms Using Association Rules

Empirically Detecting False Test Alarms Using Association Rules

A structured approach to the simulation, analysis and characterization of smartphone applications

Combating Aging with the Colt Duty Cycle Equalizer

Contact Info

Product

Resources

About