Automating the sizing of analog CMOS circuits by consideration of structural constraints

Abstract

In this paper, a method for the automatic sizing of analog integrated circuits is presented. Basic sizing rules, representing circuit knowledge, are set up before the sizing and are introduced as structural constraints into the sizing process. Systematic consideration of these structural constraints during the automatic sizing prevents pathologically sized circuits and speeds up the automatic sizing. The sizing is done with a sensitivity-based, iterative trust region method.

Deterministic Multi-Objective Optimization of Analog Circuits

“…Starting from an initial set of circuit parameters, the deterministic optimization algorithm proposed in [16] utilizes the characteristic boundary curve (CBC) algorithm to determine the correction values for circuit parameters at each optimization iteration, continuously refining the circuit parameter values to converge towards the optimal solution. However, this method suffers from some limitations.…”

“…Compared with the original CBC algorithm used to derive parameter correction, the modified GBC algorithm features much higher efficiency and can address the issue when the cost function is strongly nonlinear [17]. Moreover, since different types of design parameters have distinct sensitivities to a parameter change, calculating the parameter correction of each type of design parameters rather than the whole design parameters ensures more smooth and accurate updating of design parameters during the iterative optimization process, making it possess much better optimization efficiency and effectiveness than the work of [16].…”

Acceleration for Efficient Automated Generation of Operational Amplifiers

“…Deterministic sizing was originally proposed in [ 13 ], and it is targeted at optimizing the device sizes in a circuit with fixed biases. However, during the Op-Amp generation process, the produced circuit structures are neither sized nor biased.…”

“…In this paper, a deterministic parameter updating algorithm is proposed to enhance the efficiency and effectiveness of the deterministic sizing algorithm originally proposed in [ 13 ]. Then, a hybrid sizing method is proposed based on our deterministic parameter-updating algorithm, which can quickly figure out a decent local optimum while holding the capability of converging to a global optimum.…”

Advances in Analog Circuits

“…Figure 24 shows a differential pair circuit consisting of two nMOS transistors (m 1 and m 2 ), and an ideal current source (I b ). According with the analysis done in the previous section, the drain currents (I 1 and I 2 ) are I 1 = I 0 e κ(u−V s )/V T + I db (22) I 2 = I 0 e κ(v−V s )/V T + I db (23) 342…”