Automation of Translating Unit-Level Verification Scenarios for Test Vector Generation of SoC

The functional verification process is one of the most expensive steps in integrated circuit manufacturing. Functional coverage is the most important metric in the entire verification process. By running multiple simulations, different situations of DUT functionality can be encountered, and in this way, functional coverage fulfillment can be improved. However, in many cases it is difficult to reach specific functional situations because it is not easy to correlate the required input stimuli with the expected behavior of the digital design. Therefore, both industry and academia seek solutions to automate the generation of stimuli to reach all the functionalities of interest with less human effort and in less time. In this paper, several approaches inspired by genetic algorithms were developed and tested using three different designs. In all situations, the percentage of stimulus sets generated using well-performing genetic algorithms approaches was higher than the values that resulted when random simulations were employed. In addition, in most cases the genetic algorithm approach reached a higher coverage value per test compared to the random simulation outcome. The results confirmed that in many cases genetic algorithms can outperform constrained random generation of stimuli, that is employed in the classical way of doing verification, considering coverage fulfillment level per verification test.

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Automation of Translating Unit-Level Verification Scenarios for Test Vector Generation of SoC

Cited by 2 publications

References 18 publications

Verification of an ARM Cortex-M3 based SoC using UVM

Verification of an ARM Cortex-M3 based SoC using UVM

Coverage Fulfillment Automation in Hardware Functional Verification Using Genetic Algorithms

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