Autonomous Fault Emulation: A New FPGA-Based Acceleration System for Hardness Evaluation

Abstract

The appearance of nanometer technologies has produced a significant increase of integrated circuit sensitivity to radiation, making the occurrence of soft errors much more frequent, not only in applications working in harsh environments, like aerospace circuits, but also for applications working at the earth surface. Therefore, hardened circuits are currently demanded in many applications where fault tolerance was not a concern in the very near past. To this purpose, efficient hardness evaluation solutions are required to deal with the increasing size and complexity of modern VLSI circuits. In this paper, a very fast and cost effective solution for SEU sensitivity evaluation is presented. The proposed approach uses FPGA emulation in an autonomous manner to fully exploit the FPGA emulation speed. Three different techniques to implement it are proposed and analyzed. Experimental results show that the proposed Autonomous Emulation approach can reach execution rates higher than one million faults per second, providing a performance improvement of two orders of magnitude with respect to previous approaches. These rates give way to consider very large fault injection campaigns that were not possible in the past.

Precise fault-injections using voltage and temperature manipulation for differential cryptanalysis

“…However, we demonstrate that very high precision fault-injection is possible through voltage and temperature manipulation, as required by some of the block ciphers such as PRINCE. There are several techniques and emulators available to test and simulate the transient faults injected into secure circuits [21], [22].…”

An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors

“…[8] have been utilized. Ongil et al [20] discuss various types of fault injection techniques for medium-size non-programmable circuits. In [14], these techniques are applied to the Leon 2 processor and compared with the software-based code-emulated upsets method [13].…”

Speeding-up model-based fault injection of deep-submicron CMOS fault models through dynamic and partially reconfigurable FPGAS

“…The main idea is avoiding any communication between the host and the prototyping platform, being the FPGA responsible for applying the stimuli, injecting the faults and checking the output values. The performance and area overhead analysis of several different techniques that follow this approach was presented in [54].…”

“…Nevertheless, there is plenty of room for including different optimisations that have been successfully used for simulation-based fault injection and also for fault emulation by means of Compile-Time Reconfiguration [54], such as restoring the system's state before the last injection instead of running again till that point, or ending the emulation once the fault has been positively classified. We expect to increase the attainable acceleration well beyond two orders of magnitude by implementing some of these optimisations, by following a partial reconfiguration approach and solving some other technical problems caused by the current implementation of this first prototype.…”