AXIOM: A Scalable, Efficient and Reconfigurable Embedded Platform

Giorgi, Roberto; Procaccini, Marco; Khalili, Farnam

doi:10.23919/date.2019.8715168

Cited by 13 publications

(6 citation statements)

References 26 publications

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“…e simulator allowed us to model exactly this situation, in which the threads are distributed across several boards, through a specific execution model (called DF-reads). To that extent, the AXIOM board [11] has been designed to include a soft-IP for the routing of data (via RDMA custom messages) and the FPGA transceivers are directly connected to USB-C receptacles, so that four channels at about 18 Gbps are available for simple and inexpensive connection of up to 255 boards, without the need of an external switch [12].…”

Section: Methodsmentioning

confidence: 99%

“…As we generalized the methodology described in the previous section to the AXIOM project [10][11][12], we were able to experiment on the simulator our DF-reads execution model [15,20,21] before spending time-consuming development on the reconfigurable hardware. We show here some evaluations that are possible within the MYDSE and COTSon framework once applied to the test case of the DFreads modelling.…”

Section: Designing the Axiom Software/hardware Platformmentioning

confidence: 99%

“…ere are parameters which make simulators preferable to reach a certain level of performance, scalability, and accuracy as well as reproducibility and observability. Based on the experience of previous projects such as TERAFLUX [6,7], ERA [8,9], AXIOM [4, [10][11][12][13], and SARC [14,15], we choose to rely on the HP-Labs COTSon simulation infrastructure [16]. e key feature of COTSon that is useful in HLS design is its "functional-directed" approach, which separates the functional simulation from the timing one.…”

Section: Introductionmentioning

confidence: 99%

“…In order to illustrate our methodology, we start from a driving example related to design a simple two-way associative cache system. e methodology is then generalized by considering the case of the AXIOM project, in which this methodology was actually used to design and implement a novel data-flow architecture [20][21][22] through the development of our custom AXIOM board [11]. e contributions of this work are as follows:…”

Section: Introductionmentioning

confidence: 99%

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Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise—Designing a Computer Architecture via HLS)

Giorgi

Khalili

Procaccini

2019

International Journal of Reconfigurable Computing

Self Cite

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Translating a system requirement into a low-level representation (e.g., register transfer level or RTL) is the typical goal of the design of FPGA-based systems. However, the Design Space Exploration (DSE) needed to identify the final architecture may be time consuming, even when using high-level synthesis (HLS) tools. In this article, we illustrate our hybrid methodology, which uses a frontend for HLS so that the DSE is performed more rapidly by using a higher level abstraction, but without losing accuracy, thanks to the HP-Labs COTSon simulation infrastructure in combination with our DSE tools (MYDSE tools). In particular, this proposed methodology proved useful to achieve an appropriate design of a whole system in a shorter time than trying to design everything directly in HLS. Our motivating problem was to deploy a novel execution model called data-flow threads (DF-Threads) running on yet-to-be-designed hardware. For that goal, directly using the HLS was too premature in the design cycle. Therefore, a key point of our methodology consists in defining the first prototype in our simulation framework and gradually migrating the design into the Xilinx HLS after validating the key performance metrics of our novel system in the simulator. To explain this workflow, we first use a simple driving example consisting in the modelling of a two-way associative cache. Then, we explain how we generalized this methodology and describe the types of results that we were able to analyze in the AXIOM project, which helped us reduce the development time from months/weeks to days/hours.

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Section: Methodsmentioning

confidence: 99%

Section: Designing the Axiom Software/hardware Platformmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise—Designing a Computer Architecture via HLS)

Giorgi

Khalili

Procaccini

2019

International Journal of Reconfigurable Computing

Self Cite

View full text Add to dashboard Cite

show abstract

“…Despite the number of MPSoCs available, parallel programming in embedded system is still uncommon due to limited support in the form of user-friendly libraries and development platform. Several works attempt to support parallel programming by providing frameworks [16,17], parallel pipeline extraction [18], as well as teaching platform [19]. However, most of these platforms are rather specific in terms of their applications, languages, or program structures.…”

Section: Introductionmentioning

confidence: 99%

Multicore development environment for embedded processor in arduino IDE

et al. 2020

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Internet of things (IoT) technology has found more applications that require complex computation while still preserving power. Embedded processors as the core of the IoT system approaches the need for computation by employing a parallel processor system, namely MPSoC. While various MPSoCs hardware is widely available, there is limited software support form of user-friendly libraries and development platform. There is a need for such a platform to facilitate both the study and development of parallel embedded software. arduino as the widely used embedded development platform is yet to officially support multicore programming. This work proposes an arduino-based development environment that supports multicore programming while maintaining arduino's simple program structure, targeted at specific low-power MPSoC, the RUMPS401. The environment is fully functional, and while it targets only specific MPSoC, the proposed environment can easily be adopted to other MPSoCs with similar structures with minimal modification.

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