Dynamic random access memory (DRAM) is used as the main memory of every modern computer, due to its high density, high speed and efficient memory function. Each DRAM cell consists of one transistor, which functions as a switch for the stored charge, and one capacitor where the positive or negative electric charges corresponding to the digital 1 or 0 data are stored (see Fig. 1a). For successful operation of DRAM, a large cell capacitance ($25 fF) and low leakage current at the operation voltage (10 À7 A cm À2 or 1 fA/ cell) are required because of the following reasons; during the reading operation, stored charge is shared between the cell capacitor and bit line, which is connected to the sense amplifier. In modern DRAMs, hundreds of capacitors are connected to one bit-line so that the bit-line capacitance is usually a few ten times larger than that of the capacitor. Therefore, for a bit-line voltage variation of $100 mV through the charge sharing, which is the sensing margin of the circuit, at least $25 fF of cell capacitance is necessary. [1][2][3] The low leakage current is also essential to ensure a sufficient refresh time.In a traditional Si-based capacitor, the target cell capacitance has been achieved by increasing the surface area of the capacitor (semiconductor-insulator-semiconductor, SIS, in Fig. 1b) while the dielectric thickness is scaled down according to the design rules.[4] More recently, innovations have been made in the component materials. A metal electrode, TiN or Ru, and a dielectric material with a higher-k value (k is the relative dielectric constant) than that of the SiO 2 /Si 3 N 4 layer (k $ 6-7), such as HfO 2 (k $ 25), [5,6] ZrO 2 (k $ 40) [7] and Ta 2 O 5 (k $ 25-60) [8,9] are being explored in giga-bit scale DRAMs (metal-insulator-semiconductor, MIS, and metalinsulator-metal, MIM, in Fig. 1b). The ability of a dielectric film to store charge is conveniently represented by the equivalent oxide thickness (t ox , ¼ t phy  3.9/k, where t phy is the physical thickness of the film). The minimum achievable t ox is $0.7 nm for HfO 2 , ZrO 2 and Ta 2 O 5 which are currently being used in the DRAM industry. However, the technology road map for memory devices states that t ox less than 0.5 nm is necessary for the DRAMs with a design rule of <40 nm.[10] It is also noted that there are no known material solutions to serve this purpose. Reducing the thickness of the dielectric films with k values $20-30 to achieve the required t ox results in unacceptably high leakage currents. Therefore, a dielectric material with a higher k value is in demand. Perovskite-based dielectric films such as SrTiO 3 [11,12] and (Ba,Sr)TiO 3 [13] were reported to exhibit k values of several hundreds and therefore t ox of $0.24 nm is feasible with these materials. [14] However, growth of these films is extremely difficult with the atomiclayer-deposition (ALD) which is a method of choice for the growth of the dielectric films in microelectronic devices. A low thermal budget of 500-600 8C during the deposition and post-de...