Back-Biasing to Performance and Reliability Evaluation of UTBB FDSOI, Bulk FinFETs, and SOI FinFETs

Chang, Wen-Teng; Shih, Cheng-Ting; Wu, Jhao-Lin; Lin, Shiuan Huei; Cin, Li-Gong; Yeh, Wen–Kuan

doi:10.1109/tnano.2017.2706265

Cited by 21 publications

(10 citation statements)

References 14 publications

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“…The HCI applied equal gate (V G ) and drain (V D ) potentials because the worst case arises in FinFETs at equal biases [34]. The NBTI stress was found to cause significant degradation with V G greater than V t of 2.2 V, or V G > (V t -2.2) V. The current NBTI thus applied a stress voltage of V G = −2.5 and −2.6 V. By contrast, HCI stress voltages were found to cause significant degradation with V D = V G greater than V t of 1.1 V, or V G > (V t -1.1) V. The HCI thus used the stress voltages of −1.3 and −1.4 V. The electrical properties of the devices were measured on a logarithmic scale because the current degradation was on the logarithmic scale of time [5]. The lifetime of the devices was presumably a 10% variation of the electrical parameters, including maximum transconductance (G M,MAX ), subthreshold slope (S.S.), and V t .…”

Section: B Device Measurement and Reliability Testmentioning

confidence: 99%

“…Body bias has been used to modulate threshold voltages on ultra-thin silicon-on-insulator and buried oxide FETs. A recent study has shown that body bias can also influence the electrical properties of bulk FinFETs [5]. The V G offset swings with body bias (V B ) due to the properties of bulk FinFETs.…”

Section: A Element Analysis Of the Gate Stacks Mosmentioning

confidence: 99%

“…The aging reliability by HCI at V G = V D was measured under fresh and stress times of 1, 10, 100, 1000, 2000, 3000, 4000, and 5000 s because the damage is related to logarithmic running time [5,39]. The I D -V G curves of the p-type FinFETs at HCI of −1.3 and −1.4 V are presented in Figs.…”

Section: Hci and Nbti On P-mosfetmentioning

confidence: 99%

“…Multi-V t tuning allows designers to choose the trade-off between low power consumption and high performance [2,3]. Although post-fabrication via back biasing can modulate V t [4,5], only a limited V t range is possible.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Modifying Threshold Voltages to n- and p- Type FinFETs by Work Function Metal Stacks

Chang¹,

Li²,

Hsu³

et al. 2021

IEEE Open J. Nanotechnol.

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High-k metal gate technology improves the performance and reduces the gate leakage current of metal-oxide-semiconductor field-effect transistors (MOSFETs). This study investigated four different work function metal (WFM) stacks in the gate of fin field-effect transistors (FinFETs) on the same substrate. These devices not only successfully produced distinct levels of threshold voltages (|V t |) but also converted n-to p-type features merely by adding p-type WFM in the gate of the MOSFETs. All of the devices satisfied short-channel effects with shrinking channel length. The gate-to-body electric field induced drain leakage due to the nature of bulk FinFETs. However, the n-and p-type gate stacks presented different gate current leakage. For reliability, hot carrier injection (HCI) could have a higher reliability impact than the negative-bias temperature instability (NBTI) for p-MOSFET, although the stress voltage of HCI was roughly half that of the NBTI test. This multi-threshold voltage tuning allows designers to design CMOS and choose the trade-off between low power consumption and high performance on the same platform.

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Section: B Device Measurement and Reliability Testmentioning

confidence: 99%

Section: A Element Analysis Of the Gate Stacks Mosmentioning

confidence: 99%

Section: Hci and Nbti On P-mosfetmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Modifying Threshold Voltages to n- and p- Type FinFETs by Work Function Metal Stacks

Chang¹,

Li²,

Hsu³

et al. 2021

IEEE Open J. Nanotechnol.

Self Cite

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show abstract

“…In this Paper FinFET is developed on a buried oxide layer [19][20] with 3 fins and considering copper as gate material. For 32nm we used SiO2 as oxide layer.…”

Section: Device Structure and It's Dimensionsmentioning

confidence: 99%

Design, Simulation and Analysis of Junction Version Multi-Fin FINFET

Rao

Vandana

2021

Silicon

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This paper presents a 3-D statistical simulation study of Multi-fin junction FinFET for different technology nodes 32nm, 24 nm & 10 nm. For each and every technology node their corresponding Electrical parameters like on current (Ion), off current (Ioff), threshold voltage (Vth) are reported in the paper and also RF/Analog parameters like transconductance (gm), output conductance (gd), intrinsic gain (gm/gd) are reported. And also parameters like Electric field (E), Electron density (ne), Electron mobility (µ) which are measured across the device length are simulated. The proposed structure showed performance improvement in all the parameters when the technology node is decreased.

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Extraction of performance parameters of nanoscale SOI LDD-FinFET using a semi-analytical model of capacitance and channel potential for low-power applications

Dixit

Samajdar

2020

Appl. Phys. A

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Back-Biasing to Performance and Reliability Evaluation of UTBB FDSOI, Bulk FinFETs, and SOI FinFETs

Cited by 21 publications

References 14 publications

Modifying Threshold Voltages to n- and p- Type FinFETs by Work Function Metal Stacks

Modifying Threshold Voltages to n- and p- Type FinFETs by Work Function Metal Stacks

Design, Simulation and Analysis of Junction Version Multi-Fin FINFET

Extraction of performance parameters of nanoscale SOI LDD-FinFET using a semi-analytical model of capacitance and channel potential for low-power applications

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