Back to the Future: Current-Mode Processor in the Era of Deeply Scaled CMOS

Abstract

This paper explores the use of MOS current-mode logic (MCML) as a fast and low noise alternative to static CMOS circuits in microprocessors, thereby improving the performance, energy efficiency, and signal integrity of future computer systems. The power and ground noise generated by an MCML circuit is typically 10-100× smaller than the noise generated by a static CMOS circuit. Unlike static CMOS, whose dominant dynamic power is proportional to the frequency, MCML circuits dissipate a constant power independent of clock frequency. Although these traits make MCML highly energy efficient when operating at high speeds, the constant static power of MCML poses a challenge for a microarchitecture that operates at the modest clock rate and with a low activity factor. To address this challenge, a single-core microarchitecture for MCML is explored that exploits the C-slow retiming technique, and operates at a high frequency with low complexity to save energy. This design principle contrasts with the contemporary multicore design paradigm for static CMOS that relies on a large number of gates operating in parallel at the modest speeds. The proposed architecture generates 10-40× lower power and ground noise, and operates within 13% of the performance (i.e., 1/ExecutionTime) of a conventional, eight-core static CMOS processor while exhibiting 1.6× lower energy and 9% less area. Moreover, the operation of an MCML processor is robust under both systematic and random variations in transistor threshold voltage and effective channel length.Index Terms-Architecture-circuit codesign, energy efficient, low noise, microprocessors, MOS current-mode logic (MCML). 1063-8210

Reversible Logic Based MOS Current Mode Logic Implementation in Digital Circuits

“…The registers are synchronous circuits [21,22]. It is extensively used in almost all the applications to store the state information.…”

Design of a high-speed MCML D-Latch at 0.6 V in 45 nm CMOS technology

“…Parasitic effects in CMOS refer to unintended or undesired electrical characteristics that arise due to the inherent nature of the CMOS fabrication process or the layout of the integrated circuit. These effects can impact circuit performance, introduce errors, and degrade overall system functionality [22], [23]. CML topology is frequently used for D-Latch design where high-speed operation is required [24]- [26].…”

Simple and Accurate Model for the Propagation Delay in MCML Gates

“…MCML gates have been popular, and due to their very low switching noise, inherent robustness, and speed, they continue to be used in applications ranging from very high-speed embedded systems [25][26][27][28][29] to mixed-signal processing [30][31][32][33][34][35][36][37]. In this scenario, digital gate models with a good trade-off between simplicity and accuracy still remain a fundamental design tool for the designer.…”