Backlog Aware Low Complexity Schedulers for Input Queued Packet Switches

Dua, Vivek; Bambos, Nicholas; Olesinski,; Eberle,; Gura,

doi:10.1109/hoti.2007.4

Cited by 3 publications

(8 citation statements)

References 9 publications

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“…We compared our results with that in[8]; the latter are very similar with EiSLIP results, which are presented in Section 2.14 For generality, we give a multi-iteration description.…”

supporting

confidence: 67%

“…-Input accept: input i scans outputs onwards, starting from the one selected by A[i], and accepts the first grant. -Pointer update: iff a match, preferred or non-preferred, is achieved between input i and output j in the first scheduling round 4 …”

Section: Crossbar Scheduling Algorithmmentioning

confidence: 99%

“…On the other hand, backlog-aware (maximum weight matching, MWM) schedulers of deterministic or randomized flavor can provably sustain full throughput under longterm feasible traffic [2], [5], [3], [4], but their main drawback is hardware complexity, which increases with shrinking scheduling time. Furthermore, many of these guarantees presume impractically large VOQs, and come at the expense of very large delays.…”

Section: Introductionmentioning

confidence: 99%

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Backlog-Aware Crossbar Schedulers: A New Algorithm and its Efficient Hardware Implementation

Chrysos¹,

Dimitrakopoulos²

2008

2008 16th IEEE Symposium on High Performance Interconnects

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Crossbars switches with input queues are the common building blocks of high-speed networks, while their speed and performance critically depend on their scheduler. In this paper we combine ideas from randomized backlog-aware schedulers, and their round-robin (RR) counterparts, to propose a practical, deterministic crossbar scheduler, that: (i) achieves almost full throughput under the many adverse traffic patterns tested, using just 1 Mbyte buffer memory per input, (ii) provides deterministic delay service guarantees, (iii) yields low delays under both uniform and non-uniform load, and (iv) achieves these performances with a single iteration of an iSLIP-like algorithm. With simple extensions, the proposed crossbar scheduler is shown to distribute the bandwidth of congested links in a fair RR or WRR manner. In order to prove the efficiency of the new scheduling algorithm, we implemented in hardware a 32×32 scheduler, using a novel design for programmable-priority RR arbiters, that is significantly more area-speed efficient than present state-of-theart. The scheduler's ASIC occupies roughly 3 mm 2 , when implemented at 130nm, and gives a new crossbar match every 3.2 ns as needed for above hundred Gb/s line rates, and short packet lengths.

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“…We compared our results with that in[8]; the latter are very similar with EiSLIP results, which are presented in Section 2.14 For generality, we give a multi-iteration description.…”

supporting

confidence: 67%

Section: Crossbar Scheduling Algorithmmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Backlog-Aware Crossbar Schedulers: A New Algorithm and its Efficient Hardware Implementation

Chrysos¹,

Dimitrakopoulos²

2008

2008 16th IEEE Symposium on High Performance Interconnects

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“…Further, it is important for the schedulers to perform well with respect to metrics such as delay/ backlog, fairness, etc. It was demonstrated in [8] in the context of input queued switches that backlog aware scheduling algorithms significantly outperform algorithms which are oblivious to queue backlogs. With this motivation, we explore backlog aware scheduling algorithms for OBIG-like switches in this paper, with a view toward low complexity implementation and scalability.…”

Section: Introductionmentioning

confidence: 98%

“…Further, the performance of a crossbar is heavily dependent on the scheduling/arbitration algorithm used to match input ports to output ports. The computation of a schedule can get quite cumbersome as the switch size increases, in spite of the various low complexity algorithms which have appeared in the literature (e.g., see [4]- [8] and references therein).…”

Section: Introductionmentioning

confidence: 99%

Backlog Aware Scheduling for Large Buffered Crossbar Switches

Dua

Yolken

Bambos

et al. 2008

2008 IEEE International Conference on Communications

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A novel architecture was proposed in [1] to address scalability issues in large, high speed packet switches. The architecture proposed in [1], namely OBIG (output buffers with input groups), distributes the switch fabric across multiple chips, which communicate via high speed interconnects enabled by proximity communication (PC), a recently developed circuit technology [2]. An OBIG switch aggregates multiple input flows inside the switch fabric, thereby significantly reducing the amount of memory required for internal buffers, vis-à-vis a conventional buffered crossbar, which has buffers at every crosspoint. Thus, the OBIG architecture is promising for realizing terabit switches with hundreds of ports. This paper studies packet scheduling algorithms which help realize the potential of OBIG-like switch architectures. The emphasis here is on designing backlog aware scheduling algorithms, while ensuring desirable traits such as low computational complexity and scalability. The efficacy of the proposed scheduling algorithms with respect to performance metrics such as average delay and fairness is demonstrated via simulations under a variety of scenarios.

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