Abstract:A 10-bit successive approximation register (SAR) analog to digital converter (ADC) was designed in a 130 nm CMOS process. The reference voltage generator in the ADC is made with an array of 25 unit capacitors, in comparison to binary-weighted SAR ADCs, which would use 1024 unit capacitors. The capacitor array is controlled using a state machine whose logic was determined and automatically generated using a recursive backtracking algorithm. Schematic-level simulation results for the ADC predict an effective num… Show more
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