Bahurupi

Abstract

Computing systems have made an irreversible transition towards parallel architectures with the emergence of multi-cores. Moreover, power and thermal limits in embedded systems mandate the deployment of many simpler cores rather than a few complex cores on chip. Consumer electronic devices, on the other hand, need to support an ever-changing set of diverse applications with varying performance demands. While some applications can benefit from thread-level parallelism offered by multi-core solutions, there still exist a large number of applications with substantial amount of sequential code. The sequential programs suffer from limited exploitation of instruction-level parallelism in simple cores. We propose a reconfigurable multicore architecture, called Bahurupi, that can successfully reconcile the conflicting demands of instruction-level and thread-level parallelism. Bahurupi can accelerate the performance of serial code by dynamically forming coalition of two or more simple cores to offer increased instruction-level parallelism. In particular, Bahurupi can efficiently merge 2-4 simple 2-way out-of-order cores to reach or even surpass the performance of more complex and power-hungry 4-way or 8-way out-of-order core. Compared to baseline 2-way core, quad-core Bahurupi achieves up to 5.61 speedup (average 4.08 speedup) for embedded workloads. On an average, quad-core Bahurupi achieves 17% performance improvement and 43% improvement in energy consumption compared to 8-way out-of-order baseline core on a diverse set of embedded benchmark applications.

RETRACTED ARTICLE: Development of personalized mobile information service platform of university library based on multi-core processor and cloud computing platform

“…A processor technology Hydra integrating four MIPS83000 cores is presented in the literature. Hydra is a classic multi-core architecture, which uses the isomorphic and symmetric technology of sharing the second level cache, and also adds the multi-level communication technology of high-speed bus [11]. Since then, IBM, AMD, Intel and other large enterprises have released dual core, quad core and even higher core processors.…”

Customizable Computing

“…Because of this observation, it becomes clear that the best design depends on the number of threads that are exposed in software. To address this rigidity, core fusion [74], and other related work [31,108,115,123], propose mechanisms for implementing powerful cores out of collaborative collections of weak cores. is observation gave rise to a number of academic works that explore heterogeneous systems which feature a small group of very powerful cores on die with a large group of very efficient cores [64,71,84].…”