Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs

Zaretsky, David; Mittal, Gaurav; Dick, Robert P.; Banerjee, P.

doi:10.1109/isqed.2007.41

Cited by 15 publications

(4 citation statements)

References 15 publications

(15 reference statements)

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“…Latency and resource occupation are then obtained by synthesizing each configuration and storing the results in the library. Mathematical models can be built on top of these actual synthesis values [58], [59]. Additionally, this information can also be coupled with delays obtained after the place-and-route phase.…”

Section: E Hardware Resource Librarymentioning

confidence: 99%

A Survey and Evaluation of FPGA High-Level Synthesis Tools

Nane

Sima

Pilato

et al. 2016

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

449

182

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Abstract-High-level synthesis (HLS) is increasingly popular for the design of high-performance and energy-efficient heterogeneous systems, shortening time-to-market and addressing today's system complexity. HLS allows designers to work at a higher-level of abstraction by using a software program to specify the hardware functionality. Additionally, HLS is particularly interesting for designing FPGA circuits, where hardware implementations can be easily refined and replaced in the target device. Recent years have seen much activity in the HLS research community, with a plethora of HLS tool offerings, from both industry and academia. All these tools may have different input languages, perform different internal optimizations, and produce results of different quality, even for the very same input description. Hence, it is challenging to compare their performance and understand which is the best for the hardware to be implemented. We present a comprehensive analysis of recent HLS tools, as well as overview the areas of active interest in the HLS research community. We also present a first-published methodology to evaluate different HLS tools. We use our methodology to compare one commercial and three academic tools on a common set of C benchmarks, aiming at performing an in-depth evaluation in terms of performance and use of resources.

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Section: E Hardware Resource Librarymentioning

confidence: 99%

A Survey and Evaluation of FPGA High-Level Synthesis Tools

Nane

Sima

Pilato

et al. 2016

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

449

182

View full text Add to dashboard Cite

show abstract

“…2) Minimize T max for a given A max and θ. Notice that the minimization of θ is not possible due to the non-linearity of constraints (1)(2)(3) and the presence of θ in the LHS of the inequalities.…”

Section: F Objective Functionsmentioning

confidence: 99%

“…During HLS, performance analysis must resort to simple delay models to estimate the critical paths of the system. Such estimations may suggest chaining multiple units on the same cycle and reducing the number of execution steps or having multi-cycle operations to avoid excessively long cycle periods [3]. After synthesis, the common strategy for HLS tools is to deliver cycle-accurate static schedules that cannot be modified during RTL synthesis.…”

Section: Introductionmentioning

confidence: 99%

A hierarchical mathematical model for automatic pipelining and allocation using elastic systems

Cortadella

Petit

2017

2017 51st Asilomar Conference on Signals, Systems, and Computers

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The advent of FPGA-based accelerators has encouraged the use of high-level synthesis (HLS) for rapid prototyping and design space exploration. In this context, design optimization at behavioral level becomes a critical task for the delivery of high-quality solutions. Time elasticity opens a new avenue of optimizations that can be applied after HLS and before logic synthesis, proposing new sequential transformations that expand beyond classical retiming and enlarge the register-transfer level (RTL) exploration space. This paper proposes a mathematical model for RTL transformations that exploit elasticity to select the best implementation for each functional unit and add pipeline registers to increase performance. Two simple examples are used to validate the effectiveness and potential benefits of the model.

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“…5.14. Operation chaining is a fairly well established technique [212], [213] It is evidently clear that if the delay of a multiplier is more than or equal to the delay of three adders, the schedule in Fig. 5.14(a) will have a lower latency and input to output delay compared to the schedule in Fig 5.14(b) for the same clock period.…”

Section: B Effect Of Operation Chainingmentioning

confidence: 99%

Intelligent high level synthesis for customization on reconfigurable platforms

Sinha¹

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High level synthesis (HLS) using C/C++ has increasingly become a critical step in the realization of complex digital systems. One of the major research focus areas in this space has been to realize efficient synthesis of complex systems without violating stringent time-to-market constraints. Most of the related work cited in the literature has been mainly xi 6.2 Matrix size determination for matrix-matrix multiplication.

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Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs

Abstract: In

Cited by 15 publications

References 15 publications

A Survey and Evaluation of FPGA High-Level Synthesis Tools

A Survey and Evaluation of FPGA High-Level Synthesis Tools

A hierarchical mathematical model for automatic pipelining and allocation using elastic systems

Intelligent high level synthesis for customization on reconfigurable platforms

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