Bank Partitioning Based Adaptive Page Policy in Multi-core Memory Systems

A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore Platforms

“…To avoid this problem, Shen et al [83] proposed the use of a row-based policy, but it does not consider the inter-thread memory interference. In 2015, Fang et al [84] introduced an approach that reduces inter-thread interference without modifying the operating system. It proposed partitioning the DRAM memory banks and using an adaptive page policy that varies dynamically depending on the flow of memory access and the row buffer total hits or misses of each bank.…”

“…However, fixed-size partitions cause low cache utilization and consequently reduced performance. On the other hand, in dynamic partitioning techniques, the size of Scheduling algorithms Temporal Hardware HRT [69] Memory request throttling Temporal Software SRT/HRT [74]- [77] Predictable DRAM Controllers Predictable Controller Hardware SRT/HRT [78], [81], [82] Bank Partitioning Spatial Software AVG [60] Channel Partitioning Spatial Soft/Hard AVG [80] Page Policy Control Spatial Soft/Hard AVG [83] Page Policy Control Spatial None AVG [84] Bank Partitioning Spatial None AVG [85] Decoupled Direct Access Spatial Hardware AVG [42] Scheduling algorithms Temporal None AVG [86] Task allocation Temporal Software AVG the allocated cache partitions varies during runtime, giving high cache utilization and causing lower predictability [98]. Furthermore, cache partitioning techniques can be characterized as index-based partitioning and way-based partitioning based on the structure of a set-associative cache.…”