Baseline Stabilization in Direct Coupled Counting Systems

East, L.V.

doi:10.1063/1.1684780

Cited by 9 publications

(5 citation statements)

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“…The design of a 2-stage architecture requires both AC coupling (high-pass filtering) between stages and a baseline stabilization able to avoid the unwanted amplification of any offset voltage appearing at the output of the pre-amplifier. The DC operation point at the input of the shaping stage is forced by a baseline stabilization block, commonly used in particle detector systems due to its ability to correct baseline drifts with higher pulse rates [4,5].…”

Section: Baseline Holdermentioning

confidence: 99%

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A low-noise CMOS front-end for TOF-PET

Rolo¹,

Alves²,

Martins³

et al. 2011

J. Inst.

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An analogue CMOS front-end for triggering and amplification of signals produced by a silicon photomultiplier (SiPM) coupled to a LYSO scintillator is proposed. The solution is intended for time-of-flight measurement in compact Positron Emission Tomography (TOF-PET) medical imaging equipments where excellent timing resolution is required ( ≈ 100 ps). A CMOS 0.13 µm technology was used to implement such a front end, and the design includes preamplification, shaping, baseline holder and biasing circuitries, for a total silicon area of 500x90 µm. Waveform sampling and time-over-threshold (ToT) techniques are under study and, hence, the front-end provides fast and shaped outputs for time and energy measurements. Post layout simulation results show that, for the trigger of a single photoelectron, the time jitter due to the pre-amplifier noise can be as low as 15 ps (FWHM), for a device with a total capacitance of 70 pF. The very low input impedance of the pre-amplifier (≈ 5 Ω) allows a 1.8 ns peaking time, at the cost of 10 mW of power consumption.

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Section: Baseline Holdermentioning

confidence: 99%

“…The DC operation point at the input of the shaping stage is forced by a baseline stabilization block, commonly used in particle detector systems due to its ability to correct baseline drifts with pulse rate [5,4].…”

Section: Baseline Holdermentioning

confidence: 99%

A low-noise CMOS front-end for TOF-PET

Rolo¹,

Alves²,

Martins³

et al. 2011

J. Inst.

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show abstract

“…Due to the presence of the low-pass filter, the BLH is characterized by a very low bandwidth (has essentially zero response to each pulse) and, for this reason, conceptually differs from the feedback baseline restorer (BLR) which, in order to provide a quick baseline restoration before the arrival of following pulse, it requires a large bandwidth (it must respond to each pulse) [37-401. The BLH was used for the first time (and for the only time at our knowledge) by L. V. East [41] in 1970. Our approach consists of the realization of the non-linear buffer through a one-directional slew-rate-limited stage.…”

Section: Baseline Holder (Blh)mentioning

confidence: 99%

A generation of CMOS readout ASICs for CZT detectors

Geronimo

O’Connor

Grosholz

2000

IEEE Trans. Nucl. Sci.

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As a result of a cooperation between Brookhaven National Laboratory and eV Products a generation of high performance readout ASICs was developed. The ASICs, realized in CMOS 0.5 pm technology, are available in several different versions, single or multi-channel and with unipolar or bipolar shaper, in view of their use in research, spectroscopy, medical, safeguard and industrial applications. Four innovative circuit solutions are implemented in the ASICs: (i) a high linearity compensated continuous reset system which self-adapts to a wide range of detector leakage currents with minimum noise contribution; (ii) a high order shaper realized by using the followthe-leader feedback (FLF) approach; (iii) a class AB rail-torail output stage with high driving capability; (iv) a baseline holder (BLH) for the baseline stabilization. The basic structure of the ASICs, a description of the circuit solutions and the preliminary experimental results are reported. j

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“…For this reason, it conceptually differs from the feedback baseline restorer (BLR) which, in order to provide a quick baseline restoration before the arrival of following pulse, requires a large bandwidth (it must respond to each pulse) [12][13][14][15]. The BLH was used for the first time (and for the only time to our knowledge) by L. V. East [16] in 1970. Our novel approach consists in the way we realized the non-linear buffer through a slew-rate-limited stage.…”

Section: Description Of the Baseline Holder (Blh)mentioning

confidence: 99%

A CMOS baseline holder (BLH) for readout ASICs

Geronimo

O’Connor

Grosholz

2000

IEEE Trans. Nucl. Sci.

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As a result of a cooperation between Brookhaven National Laboratory and eV Products a generation of high performance readout ASICs was developed. One of the novel circuit solutions implemented in the ASICs is the baseline holder (BLH), a system which provides setting and stabilization of the output baseline both at low frequency and at high rate operation. The BLH is conceptually different from the baseline restorer (BLR). With a output peaking voltage 2V (10fC), a peaking time 400ns and a rate 500kHz, an asymptotic shift of the baseline < 8mV was measured.

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Baseline Stabilization in Direct Coupled Counting Systems

Cited by 9 publications

References 0 publications

A low-noise CMOS front-end for TOF-PET

A low-noise CMOS front-end for TOF-PET

A generation of CMOS readout ASICs for CZT detectors

A CMOS baseline holder (BLH) for readout ASICs

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