Basic Design of a Josephson Technology Cache Memory

We designed a superconducting random access memory (RAM) in which all component circuits can be operated with dc-bias currents. A dc-powered superconducting loop driver and a dc-powered sense circuit are effectively combined with single flux quantum (SFQ) circuits. We proposed a pipeline structure for the memory cell array composed of the dc-powered loop drivers, the dc-powered sense circuits, passive transmission lines (PTLs), and SFQ gates. This pipeline structure enables a clock operation of 10 GHz even in a large-scale RAM. An effective device structure for the RAM based on a planarized multi-layer device structure was proposed. A dc-power layer and two PTL layers were placed under the ground plane. This structure is indispensable to create the pipeline structure using PTLs. The large inductance formed in the power layer enables low power dissipation of the RAM. We found from the estimations that 10 GHz clock operation with extremely low power dissipation can be achieved even in a large-scale RAM of 1 Mbit.

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“…To operate the driver with dc power, we used a superconducting loop driver that was previously proposed by IBM [4].…”

Section: Drivermentioning

confidence: 99%

Design of all-dc-powered high-speed single flux quantum random access memory based on a pipeline structure for memory cell arrays

Nagasawa¹,

Hinode²,

Satoh³

et al. 2006

Supercond. Sci. Technol.

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“…2b) instead of Vg~2.8m V, and the output current is reduced by V g/ Vr~7. Such a difficulty has been successfully reduced by a damping resistor in the case of interferometers and more advanced circuits, but it is a consideration which cannot be ignored in the evolution of any new circuit family [34,35]. Another problem is flux trapping.…”

Section: Random Logic Circuitsmentioning

confidence: 99%

“…For example AC requires on chip power regulation and distribution. The density advantage of DC power, which avoids these extra on-chip circuits, has been discussed in connection with Josephson cache memory [35], although it has not yet demonstrated for general purpose high-speed logic. Another advantage is that the phenomenon of punchthrough associated with AC-powered latching logic is avoided.…”

Section: Direct Coupled Logic (Dcl) [46476]mentioning

confidence: 99%

“…When the personalized cells switch a combination of the currents W 1-W3 decay to zero. The interface circuit B detects the negative current transition [50] and responds by transmitting the outputs F, G, or H. This particular example is personalized to carry out the full adder function, where, Z==-Cn-j,· F==-Sn; G==-C n; and H==C n · Although the concepts and individual circuits used in this JPLA have been tested experimentally [35], no full JPLA has been tested to date.…”

Section: Josephson Programmable Logic Arrays (Jpla)mentioning

confidence: 99%

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Josephson LSI circuits

Faris

1981

IEEE Circuits Syst. Mag.

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Josephson devices combine high speed and low power dissipation which are desirable assets necessary but not sufficient to guarantee the realization of high performance computers. Adequate gain, margins and other engineering considerations also must be achieved in circuit and system designs. The evolution of random logic circuits is an example used to illustrate how this has been done, and two new DC powered logic approaches are introduced. INTRODUCTIONNumerous technological innovations introduced in recent history have resulted in improved computer performance. Since it is reasonable to assume that this trend is continuing, the what, how, and when questions related to the realization of future ultra-high performance general purpose computers have to be addressed now. This computer would probably break the 100 MIPS (millions of instructions per second) barrier and have a cycle time of r -1 ns. The entire mainframe should, therefore, be packed within a volume as small as ,....., 3000 ern", limited by the propagation velocity of the electrical signals, and should consume low enough power to ensure that an optimum operating temperature is maintained. These considerations require the switching devices to have at least three necessary physical properties in order to qualify as the main building blocks of this mainframe. These properties are: ultra-high density, low power dissipation, and high switching speeds «lOOps). Josephson junctions have received considerable attention [1][2][3][4][5][6][7] owing to their high switching speeds and low power dissipation. These two properties offer a prospect for achieving the ultra-high performance goal. Using these junctions, complex memory and logic circuits have been demonstarted [ 1,[8][9][10][11][12][13][14]. Various circuit families have evolved to do this. This paper reviews some of the design considerations which have led to this evolution. After tracing the evolution of random logic circuits, it introduces two new Josephson technology logic schemes, the functional loop logic [15,16] (FLL) and the Josephson programmable logic arrays [17], (JPLA). These circuits offer the possibility of using DC power, and some of the special advantages of DC power are discussed.

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“…Proposals for cryogenic memory date back at least to the 1970's when IBM was trying to develop a superconducting computer. 5 Progress on cryogenic memory continued in Japan after the IBM program was canceled, 6 then the field received renewed energy with the development of "single-flux-quantum" (SFQ) logic at Moscow State University in the late 1980's. 7 By the mid-1990s the Japanese had demonstrated a fully-functional 4 kbit memory array with integrated drivers to enable memory access by an SFQ processor.…”

Section: Introductionmentioning

confidence: 99%

Ferromagnetic Josephson junctions for cryogenic memory

Birge,

Madden,

Naaman

2018

Preprint

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Josephson junctions containing ferromagnetic materials have attracted intense interest both because of their unusual physical properties and because they have potential application for cryogenic memory. There are two ways to store information in such a junction: either in the amplitude of the critical current or in the ground-state phase difference across the junction; the latter is the topic of this paper. We have recently demonstrated two different ways to achieve phase control in such junctions: the first uses junctions containing two magnetic layers in a "pseudo spin valve" configuration, while the second uses junctions containing three magnetic layers with non-collinear magnetizations. The demonstration devices, however, have not yet been optimized for use in a large-scale cryogenic memory array. In this paper we outline some of the issues that must be considered to perform such an optimization, and we provide a speculative "phase-diagram" for the nickel-permalloy spin-valve system showing which combinations of ferromagnetic layer thicknesses should produce useful devices.

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Basic Design of a Josephson Technology Cache Memory

Cited by 59 publications

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Design of all-dc-powered high-speed single flux quantum random access memory based on a pipeline structure for memory cell arrays

Design of all-dc-powered high-speed single flux quantum random access memory based on a pipeline structure for memory cell arrays

Josephson LSI circuits

Ferromagnetic Josephson junctions for cryogenic memory

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