BBB: Simplifying Persistent Programming using Battery-Backed Buffers

Alshboul, Mohammad; Ramrakhyani, Prakash; Wang, William Yang; Tuck, James; Solihin, Yan

doi:10.1109/hpca51647.2021.00019

Cited by 26 publications

(29 citation statements)

References 59 publications

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“…Similarly, formalised the persistency semantics of the ARMv8 architecture declaratively; Cho et al [2021] later developed an operational ARMv8 persistency model. On the software side, there are several proposals of language-level persistency [Alshboul et al 2021;Gogte et al 2018Gogte et al , 2020Kolli et al 2017], as well as higher-level persistency approaches such as transactions [Avni et al 2015;Intel 2015;Kolli et al 2016;Shu et al 2018;Tavakkol et al 2018]. Lastly, Kokologiannakis et al [2021] recently formalised the persistency semantics of the ext4 filesystem.…”

Section: Related and Future Workmentioning

confidence: 99%

Extending Intel-x86 consistency and persistency: formalising the semantics of Intel-x86 memory types and non-temporal stores

Raad

Maranget

Vafeiadis

2022

Proc. ACM Program. Lang.

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Existing semantic formalisations of the Intel-x86 architecture cover only a small fragment of its available features that are relevant for the consistency semantics of multi-threaded programs as well as the persistency semantics of programs interfacing with non-volatile memory. We extend these formalisations to cover: (1) non-temporal writes, which provide higher performance and are used to ensure that updates are flushed to memory; (2) reads and writes to other Intel-x86 memory types, namely uncacheable, write-combined, and write-through; as well as (3) the interaction between these features. We develop our formal model in both operational and declarative styles, and prove that the two characterisations are equivalent. We have empirically validated our formalisation of the consistency semantics of these additional features and their subtle interactions by extensive testing on different Intel-x86 implementations.

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Section: Related and Future Workmentioning

confidence: 99%

Extending Intel-x86 consistency and persistency: formalising the semantics of Intel-x86 memory types and non-temporal stores

Raad

Maranget

Vafeiadis

2022

Proc. ACM Program. Lang.

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“…For instance, the ISA in x86 systems [10] provides CLWB and CLFLUSHOPT to flush a cache line into (persistent) memory and SFENCE to ensure previous store or flush operations are visible before any store or flush operations following the SFENCE. Similar flush (e.g., DC CVAP) and fence (e.g., DSB) instructions are available in ARM [1,34]. Alternatively, programmers can use non-temporal stores to directly write data to PM bypassing CPU caches [63].…”

Section: Background and Motivation 21 Crash Consistency In Pm Program...mentioning

confidence: 99%

“…This failure model of PM is based on the assumption that CPU registers and caches are volatile, which is commonly used in real hardware (e.g., Intel Optane PM with asynchronous DRAM refresh (ADR) [24,63]), computer systems [28,32,67,70], and PM-specific testing tools [15,19,35,45]. Enhancing CPU caches with durability is possible but requires hardware modifications [1,68] or additional intel-specific extended ADR (eADR) support [50], which are not necessary for PM programming (refer to ğ6.6 for more discussions about eADR). Hence, in the context of this paper, following previous work [15, 19, 20, 35ś37, 45], we assume that CPU caches are not included in the persistent domain.…”

Section: Assumptions and Definitionsmentioning

confidence: 99%

“…When the eADR feature is available and enabled on a PM platform (requiring Intel Optane Persistent Memory 200 Series, the third generation Intel Xeon Scalable Processor, and OEM supports for additional batteries[50]), CPU caches become persistent domains protected by batteries. As a result, the cache line flush primitives are not required for PM programming[1,50], thus avoiding PM Inter-thread Inconsistency. However, for PM Synchronization Inconsistency identified by PMRace, corresponding PM Execution Context Bugs still occur on eADR-based PM systems, since the unreleased locks and other exclusive resources in PM survive system crashes.…”

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confidence: 99%

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Efficiently detecting concurrency bugs in persistent memory programs

Chen

Hua

Zhang

et al. 2022

Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

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Due to the salient DRAM-comparable performance, TB-scale capacity, and non-volatility, persistent memory (PM) provides new opportunities for large-scale in-memory computing with instant crash recovery. However, programming PM systems is error-prone due to the existence of crash-consistency bugs, which are challenging to diagnose especially with concurrent programming widely adopted in PM applications to exploit hardware parallelism. Existing bug detection tools for DRAM-based concurrency issues cannot detect PM crash-consistency bugs because they are oblivious to PM operations and PM consistency. On the other hand, existing PM-specific debugging tools only focus on sequential PM programs and cannot effectively detect crash-consistency issues hidden in concurrent executions.In order to effectively detect crash-consistency bugs that only manifest in concurrent executions, we propose PMRace, the first PM-specific concurrency bug detection tool. We identify and define two new types of concurrent crash-consistency bugs: PM Interthread Inconsistency and PM Synchronization Inconsistency. In particular, PMRace adopts PM-aware and coverage-guided fuzz testing to explore PM program executions. For PM Inter-thread Inconsistency, which denotes the data inconsistency hidden in thread interleavings, PMRace performs PM-aware interleaving exploration and thread scheduling to drive the execution towards executions that reveal such inconsistencies. For PM Synchronization Inconsistency between persisted synchronization variables and program data, PM-Race identifies the inconsistency during interleaving exploration. The post-failure validation reduces the false positives that come from custom crash recovery mechanisms. PMRace has found 14 bugs (10 new bugs) in real-world concurrent PM systems including PM-version memcached.

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“…2 The CPU then copies the data from host DRAM to the NVM. 3 The CPU finally guarantees the persistence of the data to PM by evicting contents from caches. We refer to this three step process as CPU-Assisted Persistence or CAP.…”

Section: The Case For Gpm and Its Designmentioning

confidence: 99%

GPM: leveraging persistent memory from a GPU

Pandey¹,

Kamath²,

Basu³

2022

Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

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The GPU is a key computing platform for many application domains. While the new non-volatile memory technology has brought the promise of byte-addressable persistence (a.k.a., persistent memory, or PM) to CPU applications, the same, unfortunately, is beyond the reach of GPU programs.We take three key steps toward enabling GPU programs to access PM directly. First, enable direct access to PM from within a GPU kernel without needing to modify the hardware. Next, we demonstrate three classes of GPU-accelerated applications that benefit from PM. In the process, we create a workload suite with nine such applications. We then create a GPU library, written in CUDA, to support logging, checkpointing, and primitives for native persistence for programmers to easily leverage PM. CCS CONCEPTS• Computer systems organization → Processors and memory architectures.

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BBB: Simplifying Persistent Programming using Battery-Backed Buffers

Cited by 26 publications

References 59 publications

Extending Intel-x86 consistency and persistency: formalising the semantics of Intel-x86 memory types and non-temporal stores

Extending Intel-x86 consistency and persistency: formalising the semantics of Intel-x86 memory types and non-temporal stores

Efficiently detecting concurrency bugs in persistent memory programs

GPM: leveraging persistent memory from a GPU

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