2011
DOI: 10.1109/tim.2011.2128570
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Behavioral Modeling of IC Memories From Measured Data

Abstract: This paper addresses the generation of behavioral models of digital ICs for signal and power integrity simulations. The proposed models are obtained by external measurements carried out at the device ports only and by the combined application of specialized state-of-the-art modeling techniques. The present approach exploits a behavioral formulation, leading to models reproducing all the behavior of the IC ports as the I/O buffers and the core power delivery network. The modeling procedure is demonstrated for a… Show more

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Cited by 8 publications
(12 citation statements)
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“…Due to process variations, the thickness and permittivity of the substrate, as well as the gap between the two coupled lines, are assumed as Gaussian distributed random variables with standard deviations 10% of their nominal values, respectively. The system is driven at port 1 by an I/O transceiver of a 512 Mb Flash memory chip, which is implemented in SPICE by means of an equivalent and efficient behavioral macromodel [13] and generates a pulse with a rise time of 1 ns. Ports 3 to 6 are connected to diodes and linear lumped elements.…”
Section: Numerical Examplementioning
confidence: 99%
“…Due to process variations, the thickness and permittivity of the substrate, as well as the gap between the two coupled lines, are assumed as Gaussian distributed random variables with standard deviations 10% of their nominal values, respectively. The system is driven at port 1 by an I/O transceiver of a 512 Mb Flash memory chip, which is implemented in SPICE by means of an equivalent and efficient behavioral macromodel [13] and generates a pulse with a rise time of 1 ns. Ports 3 to 6 are connected to diodes and linear lumped elements.…”
Section: Numerical Examplementioning
confidence: 99%
“…According to (Stievano et al, 2011a;, the model for the core power supply of ICs is defined by a simplified -physically inspired -circuit equivalent that attempts to describe the different blocks involved in the power delivery network of a digital IC. A common assumption in these approaches is the description of the core power delivery network of the IC by means of a Norton equivalent like the one of Fig.…”
Section: Core Power Delivery Networkmentioning
confidence: 99%
“…Once the switching activity current i SS (t) is recorded, the measured waveform needs to be suitably processed for de-embedding the effects of the measurement setup. The readers should refer to (Stievano et al, 2011a) for additional details and a more comprehensive discussion of the post-processing for the same example test chip of this work.…”
Section: Core Power Delivery Networkmentioning
confidence: 99%
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