Benchmark Tests for MOSFET Compact Models With Application to the PSP Model

UTSOI2: A complete physical compact model for UTBB and independent double gate MOSFETs

“…In particular, the C(V) characteristic in Fig.11 illustrates the accuracy of the model for back biases as high as 10V applied on a device with a 25nm Box. Furthermore, this model is compliant with continuity, symmetry and robustness criteria of standard compact models [16], as shown in Fig.12 (left). Finally, to illustrate the suitability of UTSOI2 for circuit simulations, Fig.12 …”

Surface-potential-based compact modeling of dynamically depleted SOI MOSFETs

“…The RF and mixed signal design applications of MOS technology resulted in several stringent requirements (''benchmarks") imposed on the qualitative behavior of the compact MOSFET models [34][35][36]. The PSP-SOI DD model has been subjected to all standard and newly developed benchmarks including symmetry tests, slope-ratio test, tree-top test, etc.…”

“…The PSP-SOI DD model has been subjected to all standard and newly developed benchmarks including symmetry tests, slope-ratio test, tree-top test, etc. [36]. Here we present results of the two recently developed symmetry tests for DC and AC operation of MOS transistors [35].…”

“…Fig. 16 shows the test circuit we used in our benchmark symmetry tests [35,36]. The results are presented in Fig.…”

“…Drain currents calculated from the complete charge-sheet model(28) and from symmetrically linearized charge-sheet model(36). used in the calculation are tox¼ 2 nm; NA ¼ 5 Â 10 17 cm À3 ; tsi ¼ 40 nm; t box ¼ 200 nm; V f FB ¼ À0:8 V and V b FB ¼ 0 V.Front surface potential along the channel for the complete and symmetrically linearized charge-sheet model.…”