Benchmarking a New Paradigm: Experimental Analysis and Characterization of a Real Processing-in-Memory System

Gómez-Luna, Juan; Hajj, I.N.; Fernández, Iván; Giannoula, Christina; Oliveira, Geraldo F.; Mutlu, Onur

doi:10.1109/access.2022.3174101

Cited by 69 publications

(39 citation statements)

References 222 publications

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“…SpMV performs indirect memory references as a result of storing the sparse matrix in a compressed format, and irregular memory accesses to the input vector due to the sparsity pattern of the input matrix [6,13,27]. Therefore, in commodity processor-centric systems, SpMV is a primarily memorybandwidth-bound kernel for the majority of real sparse matrices, and is bottlenecked by data movement between memory and processors [6,9,10].…”

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confidence: 99%

“…PIM moves computation close to application data by equipping memory chips with processing capabilities [1,14,15]. To provide large aggregate memory bandwidth for the in-memory processors, several manufacturers have already started to commercialize nearbank PIM designs [1,9,10,19,20]. Near-bank PIM designs tightly couple a PIM core with each DRAM bank, exploiting bank-level parallelism to expose high on-chip memory bandwidth of standard DRAM to processors.…”

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confidence: 99%

“…Near-bank PIM designs tightly couple a PIM core with each DRAM bank, exploiting bank-level parallelism to expose high on-chip memory bandwidth of standard DRAM to processors. Three real near-bank PIM architectures are Samsung's FIMDRAM [19], SK hynix's GDDR6-AiM [20] and the UPMEM PIM system [1,9,10].…”

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confidence: 99%

“…Most real near-bank PIM architectures [1,9,10,19,20] support several PIM-enabled memory chips connected to a host CPU via memory channels. Each memory chip comprises multiple lowpower PIM cores with relatively low computation capability [9,10], and each of them is located close to a DRAM bank [9,10,19,20]. Each PIM core can access data located on its local DRAM bank, and typically there is no direct communication channel among PIM cores.…”

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confidence: 99%

“…As such, they are a very promising computing platform to accelerate memory-bound kernels. Recent works leverage near-bank PIM architectures to provide high performance and energy benefits on bioinformatics [5,9,10], skyline computation [22], compression [11] and neural network [9,10,16,19] kernels. A recent study [9,10] provides PrIM benchmarks [25], which are a collection of 16 kernels for evaluating near-bank PIM architectures.…”

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confidence: 99%

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Towards Efficient Sparse Matrix Vector Multiplication on Real Processing-In-Memory Systems

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Gómez-Luna³

et al. 2022

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confidence: 99%

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confidence: 99%

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confidence: 99%

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Towards Efficient Sparse Matrix Vector Multiplication on Real Processing-In-Memory Systems

Giannoula¹,

Fernandez²,

Gómez-Luna³

et al. 2022

Preprint

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Energy Efficiency Impact of Processing in Memory: A Comprehensive Review of Workloads on the UPMEM Architecture

Falevoz,

Legriel

2024

Lecture Notes in Computer Science

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Processing-in-Memory (PIM) architectures have emerged as a promising solution for data-intensive applications, providing significant speedup by processing data directly within the memory. However, the impact of PIM on energy efficiency is not well characterized. In this paper, we provide a comprehensive review of workloads ported to the first PIM product available on the market, namely the UPMEM architecture, and quantify the impact on each workload in terms of energy efficiency. Less than the half of the reviewed papers provide insights on the impact of PIM on energy efficiency, and the evaluation methods differ from one paper to the other. To provide a comprehensive overview, we propose a methodology for estimating energy consumption and efficiency for both the PIM and baseline systems at data center level, enabling a direct comparison of the two systems. Our results show that PIM can provide significant energy savings for data intensive workloads. We also identify key factors that impact the energy efficiency of UPMEM PIM, including the workload characteristics. Overall, this paper provides valuable insights for researchers and practitioners looking to optimize energy efficiency in data-intensive applications using UPMEM PIM architecture.

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High-performance and balanced parallel graph coloring on multicore platforms

et al. 2022

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Graph coloring is widely used to parallelize scientific applications by identifying subsets of independent tasks that can be executed simultaneously. Graph coloring assigns colors the vertices of a graph, such that no adjacent vertices have the same color. The number of colors used corresponds to the number of parallel steps in a real-world end-application. Therefore, the total runtime of the graph coloring kernel adds to the overall parallel overhead of the real-world end-application, whereas the number of the vertices of each color class determines the number of the independent concurrent tasks of each parallel step, thus affecting the amount of parallelism and hardware resource utilization in the execution of the real-world end-application. In this work, we propose a high-performance graph coloring algorithm, named ColorTM, that leverages Hardware Transactional Memory (HTM) to detect coloring inconsistencies between adjacent vertices. ColorTM detects and resolves coloring inconsistencies between adjacent vertices with an eager approach to minimize data access costs, and implements a speculative synchronization scheme to minimize synchronization costs and increase parallelism. We extend our proposed algorithmic design to propose a balanced graph coloring algorithm, named BalColorTM, with which all color classes include almost the same number of vertices to achieve high parallelism and resource utilization in the execution of the real-world end-applications. We evaluate ColorTM and BalColorTM using a wide variety of large real-world graphs with diverse characteristics. ColorTM and BalColorTM improve performance by 12.98$$\times$$ × and 1.78$$\times$$ × on average using 56 parallel threads compared to prior state-of-the-art approaches. Moreover, we study the impact of our proposed graph coloring algorithmic designs on a popular end-application, i.e., Community Detection, and demonstrate the ColorTM and BalColorTM can provide high-performance improvements in real-world end-applications across various input data given.

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Benchmarking a New Paradigm: Experimental Analysis and Characterization of a Real Processing-in-Memory System

Cited by 69 publications

References 222 publications

Towards Efficient Sparse Matrix Vector Multiplication on Real Processing-In-Memory Systems

Towards Efficient Sparse Matrix Vector Multiplication on Real Processing-In-Memory Systems

Energy Efficiency Impact of Processing in Memory: A Comprehensive Review of Workloads on the UPMEM Architecture

High-performance and balanced parallel graph coloring on multicore platforms

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