Benchmarking High Bandwidth Memory on FPGAs

Wang, Zeke; Huang, Hongjing; Zhang, Jie; Alonso, Gustavo

doi:10.48550/arxiv.2005.04324

Cited by 2 publications

(2 citation statements)

References 37 publications

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“…The experimental setup for testing our design (Fig. 5) includes a benchmark module similar to Shuhai [13] and based on the Repetitive Sequential Traversal (RST) access pattern (We call it RSTBenchmark) and a MicroBlaze soft-core processor to control the benchmark IP. Since we emphasize on the MT performance in this paper, only BMT subsystem is tested separately.…”

Section: Experimental Setup and Resultsmentioning

confidence: 99%

HMT: A Hardware-Centric Hybrid Bonsai Merkle Tree Algorithm for High-Performance Authentication

Shadab

Zou

Gandham

et al. 2022

Proceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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Bonsai Merkle tree (BMT) is a widely used data structure for authenticating data/metadata in a secure computing system. However, the predominantly recursive and sequential nature of traditional BMT algorithms make them challenging to implement with Field-Programmable Gate Array (FPGA) in modern heterogeneous computing platforms. In this work, we introduce HMT, a hardware-friendly implementation methodology for BMT that enables the verification and update processes to function independently, as well as saves additional write-backs by making the update conditions more flexible compared to previous algorithms. The methodology of HMT contributes both novel algorithm revisions and innovative hardware techniques to implementing BMT. Our empirical performance measurements have demonstrated that HMT can achieve up to 7x improvement in bandwidth and 4.5x reduction in latency over the baseline.

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Section: Experimental Setup and Resultsmentioning

confidence: 99%

HMT: A Hardware-Centric Hybrid Bonsai Merkle Tree Algorithm for High-Performance Authentication

Shadab

Zou

Gandham

et al. 2022

Proceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

View full text Add to dashboard Cite

show abstract

“…When compared to the popular GPU accelerators, FPGAs excel for the following reasons: (1) The on-chip memory capacity of FPGAs is much higher (360×) than that of GPUs (i.e., 35 MB in Xilinx Alveo U200 vs. 96 KB in V100). The FPGA on-chip memory features its high memory bandwidth (31 TB/s) and low access latency (single clock cycle), enabling higher throughput and lower latency design [21][22][23][24][25][26][27][28]. With more on-chip memory size, we can achieve a better computation to communication (CTC) ratio for the same operations, i.e., matrix multiply and matrix add.…”

Section: Hardware Accelerator Design and Scheduling Algorithmmentioning

confidence: 99%

A Length Adaptive Algorithm-Hardware Co-design of Transformer on FPGA Through Sparse Attention and Dynamic Pipelining

Peng,

Huang,

Chen

et al. 2022

Preprint

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Transformers are considered one of the most important deep learning models since 2018, in part because it establishes state-of-the-art (SOTA) records and could potentially replace existing Deep Neural Networks (DNNs). Despite the remarkable triumphs, the prolonged turnaround time of Transformer models is a widely recognized roadblock. The variety of sequence lengths imposes additional computing overhead where inputs need to be zero-padded to the maximum sentence length in the batch to accommodate the parallel computing platforms. This paper targets the field-programmable gate array (FPGA) and proposes a coherent sequence length adaptive algorithm-hardware co-design for Transformer acceleration. Particularly, we develop a hardware-friendly sparse attention operator and a length-aware hardware resource scheduling algorithm. The proposed sparse attention operator brings the complexity of attention-based models down to linear complexity and alleviates the off-chip memory traffic. The proposed length-aware resource hardware scheduling algorithm dynamically allocates the hardware resources to fill up the pipeline slots and eliminates bubbles for NLP tasks. Experiments show that our design has very small accuracy loss and has 80.2 × and 2.6 × speedup compared to CPU and GPU implementation, and 4 × higher energy efficiency than state-of-the-art GPU accelerator optimized via CUBLAS GEMM.

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Benchmarking High Bandwidth Memory on FPGAs

Cited by 2 publications

References 37 publications

HMT: A Hardware-Centric Hybrid Bonsai Merkle Tree Algorithm for High-Performance Authentication

HMT: A Hardware-Centric Hybrid Bonsai Merkle Tree Algorithm for High-Performance Authentication

A Length Adaptive Algorithm-Hardware Co-design of Transformer on FPGA Through Sparse Attention and Dynamic Pipelining

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