Benchmarking of Standard-Cell Based Memories in the Sub-$V_{\rm T}$ Domain in 65-nm CMOS Technology

Abstract

Abstract-In this paper, standard-cell based memories (SCMs) are proposed as an alternative to full-custom sub-V T SRAM macros for ultra-low-power systems requiring small memory blocks. The energy per memory access as well as the maximum achievable throughput in the sub-V T domain of various SCM architectures are evaluated by means of a gate-level sub-V T characterization model, building on data extracted from fully placed, routed, and back-annotated netlists. The reliable operation at the energy-minimum voltage of the various SCM architectures in a 65-nm CMOS technology considering within-die process parameter variations is demonstrated by means of Monte Carlo circuit simulation. Finally, the energy per memory access, the achievable throughput, and the area of the best SCM architecture are compared to recent sub-V T SRAM designs.

A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS

“…Compared to a previous study on SCMs considering only commercially available standard-cell libraries [5], designing merely one custom standard-cell (3-state-enabled low-leakage latch) cuts the leakage power into half while maintaining the same silicon area. Table II shows the best (in terms of access energy and leakage power) memories in 65nm CMOS reported to date.…”

“…While bitcell read-failures and write-failures are avoided by using a read buffer and by disabling the bitcell-internal keeper, respectively, hold-failures limit V DD down-scaling [5]. To assess the minimum V DD required to hold data (V DDhold ), the minimum V DD for which both static noise margin (SNM) values (corresponding to data '1' and '0', or, in other words, to top and bottom eye of the butterfly curve [9]) are still positive are extracted from a 1k-point Monte Carlo (MC) circuit simulation (accounting for within-die (WID) parametric variations, in the TT corner, at 27…”

“…The reported clock frequencies are suitable for a wide range of biomedical applications, while most previously reported sub-V T SRAMs are overdesigned. Even the silicon area of SCMs is smaller compared to sub-V T SRAM hardmacros for storage capacities of up to several kb, due to less area for peripheral circuits [5]. For several tens of kb, an area-increase of roughly 4X [5], stemming from the larger bitcell, is acceptable for the benefit of the clearly lower leakage power and access energy.…”

“…Standard-cell based memories (SCMs) are an interesting alternative to full-custom sub-V T SRAM macros in order to significantly reduce the design effort, ensure reliability, and even reduce the area cost for storage capacities smaller than a few kb [5]. However, as many SRAM macros [1][2][3], the SCMs presented in [5] suffer from high leakage currents, as they are implemented with latches from a commercial standard-cell library, which is primarily optimized for speed, but not for leakage.…”

“…Relying on the fact that the bitcells (latches) together with the read multiplexers consume almost the totality of the leakage power of SCMs, a single custom-designed standard-cell, namely a low-leakage D-latch with 3-state output buffer, is integrated in the automated SCM compilation flow. As opposed to previous work [6], the proposed SCM design flow does not restrict the leakage minimization to the bitcells, but extends it to the peripheral circuits by using a 3-state read logic, accepting a speed degradation of the otherwise rather fast SCMs [5] for the benefit of lower leakage.…”