Benchmarking the cache memory effect

Abstract

A new performance model of the memory hierarchy is first introduced, which describes all possible scenarios for the calculation process, including the important case when the cache memory is bypassed. A detailed study of each scenario is then given along with the derivation of corresponding formulae. In these formulae the cache load time associated with the penalty which must be paid to transfer data between the main memory and the cache is also taken into account. A two-parameter linear model for performance characterisation of cache memory effect is introduced. The double-performance parameter, n2, is defined to describe the performance degradation for problem sizes that do not fit into the cache memory. This parameter determines the problem size required to preserve twice the asymptotic performance. Excellent agreement is shown between the estimated performance figures and several benchmark measurements on iPSC/860. * The results presented here were previously published in an extended version of this article which appeared in Supercomputer 63, vol XI (5), 1995. They are re-produced with kind permission of ASFRA BV, The Netherlands.