BER-optimal analog-to-digital converters for communication links

Abstract

In this thesis, we propose BER-optimal analog-to-digital converters (ADC) where quantization levels and thresholds are set non-uniformly to minimize the bit-error rate (BER). This is in contrast to present-day ADCs which act as transparent waveform preservers. We define the ADC shaping gain metric in order to quantify the improvements. Simulations for various communication channels show that the BER-optimal ADC achieves shaping gains that range from 2.5 dB for channels with low intersymbol interference (ISI) to more than 30 dB for channels with high ISI. Moreover, a 3 bit BER-optimal ADC achieves at least as low a BER as a 4 bit uniform ADC. For flash converters, this corresponds to a power reduction by 2×. Look-up table based equalizers compatible with BER-optimal ADCs are shown to reduce the power up to 47% and the area up to 66% in a 45 nm CMOS process. The shaping gain due to BER-optimal ADCs can be exploited to lower peak transmit swings at the transmitter or decrease power consumption of the ADC.

Space-time slicer architectures for analog-to-information conversion in channel equalizers

“…We propose a different metric (more sensitive to the uncoded BER) and an iterative algorithm for optimizing our space-time slicer, choosing both sampling times and amplitude thresholds. The advantage of non-uniform thresholds for equalization has been reported in [8] [9]. We arrive at similar conclusions, as discussed in Section IV of the paper, but our results are more general with designs involving non-uniform thresholds spread across time.…”

“…Note that the configurations obtained are a mixture of the two extreme structures of a flash ADC and 1-bit measurements. Also note the higher concentration of the slicers near the zero threshold (similar to the better performing non-uniform ADC thresholds found in [9][8]). We observe that the generalized structure with 14 slicers results in 3-5dB SNR gains at the BER of 10 −3 compared to a conventional 4-bit uniform ADC that uses 15 slicers.…”

“…Reference [6] discusses channel estimation with coarsely quantized samples. A number of recent papers [7] [8] [9] consider the problem of equalization with low-precision analog front ends, and propose methods for designing ADC quantizer levels. The emphasis in all of these papers remains on designing multiple slicer thresholds for a given sample, rather than dispersing the slicers over time as we allow.…”

“…We arrive at similar conclusions, as discussed in Section IV of the paper, but our results are more general with designs involving non-uniform thresholds spread across time. The DSP algorithms used in these references are simple DFE equalizers: 5 feedback taps and a single feedforward tap in [8], which is only applicable to channels with limited precursor intersymbol interference (ISI), and 2-3 feedforward taps with 2 feedback taps in [9]. Further, the numerical evaluations in [8][9] focus on a high SNR regime with very low BERs (∼ 10 −12 ).…”

Low-precision analog-to-digital conversion and mutual information in channels with memory

“…Instead, we are interested in the mutual information between the transmitted bits and the sequence of quantizer outputs as a figure of merit. In related work, [4] optimized the A/D converter levels for a particular receiver structure with the uncoded bit error rate (BER) as the cost function to be minimized. The authors of [5] study the impact of the relative sampling phases of a time-interleaved sampler on the mutual information between the transmitted bits and the outputs of the different paths of the converters; however, the quantization step is not included in the analysis.…”