Best Practices for Scalable Power Measurement and Control

Walker, Scott Mervyn; McFadden, Marty

doi:10.1109/ipdpsw.2016.91

Cited by 6 publications

(2 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For tool stability reason, attention to detail/accuracy, and overlap with our needs, we settle on the use of the MPI API 4 . Furthermore, as auxiliary tools we rely on RRZE's Likwid [42] for frequency scaling 5 and LLNL's msr-safe [43] for allowing access to CPU model-specific registers. An overview of (raw) metrics which we extract with these tools for the benchmarks, listed in Section II-B, is shown in Table III.…”

Section: B Metrics and Measurement Toolsmentioning

confidence: 99%

Double-Precision FPUs in High-Performance Computing: An Embarrassment of Riches?

Domke

Matsumura

Wahib

et al. 2019

2019 IEEE International Parallel and Distributed Processing Symposium (IPDPS)

View full text Add to dashboard Cite

Among the (uncontended) common wisdom in High-Performance Computing (HPC) is the applications' need for large amount of double-precision support in hardware. Hardware manufacturers, the TOP500 list, and (rarely revisited) legacy software have without doubt followed and contributed to this view.In this paper, we challenge that wisdom, and we do so by exhaustively comparing a large number of HPC proxy applications on two processors: Intel's Knights Landing (KNL) and Knights Mill (KNM). Although similar, the KNL and KNM architecturally deviate at one important point: the silicon area devoted to doubleprecision arithmetics. This fortunate discrepancy allows us to empirically quantify the performance impact in reducing the amount of hardware double-precision arithmetic.Our analysis shows that this common wisdom might not always be right. We find that the investigated HPC proxy applications do allow for a (significant) reduction in double-precision with little-to-no performance implications. With the advent of a failing of Moore's law, our results partially reinforce the view taken by modern industry (e.g., upcoming Fujitsu ARM64FX) to integrate hybrid-precision hardware units.

show abstract

Section: B Metrics and Measurement Toolsmentioning

confidence: 99%

Double-Precision FPUs in High-Performance Computing: An Embarrassment of Riches?

Domke

Matsumura

Wahib

et al. 2019

2019 IEEE International Parallel and Distributed Processing Symposium (IPDPS)

View full text Add to dashboard Cite

show abstract

“…The profiler maintains the tracing information in a memory area shared among all the processes. The profiler exploits the MSR SAFE kernel driver to access the performance registers using the batch mode [45] to reduce the overhead. Moreover, it uses Intel Running Average Power Limit (RAPL) registers to monitor the energy/power consumed by the CPU and DRAM.…”

Section: Profilermentioning

confidence: 99%

COUNTDOWN Slack: a Run-time Library to Reduce Energy Footprint in Large-scale MPI Applications

Cesarini¹,

Bartolini²,

Borghesi³

et al. 2019

Preprint

View full text Add to dashboard Cite

The power consumption of supercomputers is a major challenge for system owners, users, and society. It limits the capacity of system installations, it requires large cooling infrastructures, and it is the cause of a large carbon footprint. Reducing power during application execution without changing the application source code or increasing time-to-completion is highly desirable in real-life high-performance computing scenarios.The power management run-time frameworks proposed in the last decade are based on the assumption that the duration of communication and application phases in an MPI application can be predicted and used at run-time to trade-off communication slack with power consumption. In this manuscript, we first show that this assumption is too general and leads to mispredictions, slowing down applications, thereby jeopardizing the claimed benefits. We then propose a new approach based on (i) the separation of communication phases and slack during MPI calls and (ii) a timeout algorithm to cope with the hardware power management latency, which jointly makes it possible to achieve performance-neutral power saving in MPI applications without requiring labor-intensive and risky application source code modifications. We validate our approach in a tier-1 production environment with widely adopted scientific applications. Our approach has a time-to-completion overhead lower than 1%, while it successfully exploits slack in communication phases to achieve an average energy saving of 10%. If we focus on a largescale application runs, the proposed approach achieves 22% energy saving with an overhead of only 0.4%. With respect to state-of-the-art approaches, COUNTDOWN Slack is the only that always leads to an energy saving with negligible overhead (< 3%).

show abstract

Analysis of the efficiency characteristics of the first High-Temperature Direct Liquid Cooled Petascale supercomputer and its cooling infrastructure

Shoukourian

Wilde

Huber

et al. 2017

Journal of Parallel and Distributed Computing

View full text Add to dashboard Cite

Best Practices for Scalable Power Measurement and Control

Cited by 6 publications

References 8 publications

Double-Precision FPUs in High-Performance Computing: An Embarrassment of Riches?

Double-Precision FPUs in High-Performance Computing: An Embarrassment of Riches?

COUNTDOWN Slack: a Run-time Library to Reduce Energy Footprint in Large-scale MPI Applications

Analysis of the efficiency characteristics of the first High-Temperature Direct Liquid Cooled Petascale supercomputer and its cooling infrastructure

Contact Info

Product

Resources

About