Between-core vector overlapping for test cost reduction in core testing

Concurrent Core Testing for SOC Using Merged Test Set and Scan Tree

“…Table 6 shows the comparison of test data compression with previously published results. Note that it is difficult to compare with [12] and [13] directly, because they used different test sets for experiments. To validate the effectiveness of the proposed approach, we therefore select test compression techniques [9]- [11] for fair comparison since all these methods use the same MINTEST sets.…”

“…As far as output response analyzer (ORA) is concerned, as done in [12], [13], a time-based compactor, e.g., MISR can be used to compact test responses and eventually delivers the signature to ATE using only one output pin. Alternatively, a space-based compactor with X-tolerant capability [17] can also be used.…”

“…On the other hand, this principle guarantees that all CUTs can share one capture cycle for one applied test vector, thus greatly simplifying the design of control logic for generating the capture sequence. The employed method of one capture for one merged test vector is distinct from the method of [13] in which multiple vectors from one test set can be overlapped with one target vector at different bit positions, which will complicate the design of control logic.…”

“…Moreover, it is difficult for this method to find the optimal virtual circuit and corresponding scan chain architecture to achieve the largest reduction in test cost because there are too many possibilities for constructing the virtual circuit [12]. More recently, an "overlapped vector" method was proposed in [13] where the overlapped vectors were broadcasted to multiple cores using an input pin. While this method achieves significant reduction in test cost without use of any additional ATPG, it suffers from the complex hardware structure in which an FIFO queue and an additional ATE channel have to be used to retrieve the original test vectors from the overlapped vectors.…”

“…Finally, all cores in the scan tree can be tested simultaneously using only one test input. In comparison with previous work in [13], the advantages of the proposed approach are that the scan tree is easy to construct with low hardware overhead and it does not require additional ATE channel. Furthermore, the approach does not need to run any special test generation and can be used in conjunction with general compression/decompression techniques to further reduce test cost.…”