Beyond UVM for practical SoC verification

Yun, Young-Nam; Kim, Jae‐Beom; Kim, Namdo; Min, Byeong

doi:10.1109/isocc.2011.6138671

Cited by 56 publications

(14 citation statements)

References 2 publications

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“…In [9], authors have proposed an idea for verifying SOC based on UVM. Similarly, in [10] authors have introduced verification of a PCI bus using SystemC, but for novice verification engineers learning a new methodology and then creating a verification environment may require more time.…”

Section: Related Workmentioning

confidence: 99%

Accelerating functional verification of PCI express endpoint by emulating host system using PCI express core

Badhe

Kulkarni

Gadre

2014

2014 First International Conference on Computational Systems and Communications (ICCSC)

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PCI Express is a high-performance I/O bus protocol. The PCI Express protocol provides higher bandwidth than the legacy buses that makes PCI Express as an ideal choice for a wide variety of applications such as Network Interface, Graphics Accelerators, and Storage Controllers (SSD). The PCI Express protocol supports many features to improve performance of I/O Bus, so verification of a design based on this protocol is a very long and time consuming process. As an application based on the PCI Express protocol becomes more and more complex the verification complexity increases many folds.PCI Express Endpoint device communicates with the host (Processor/Memory) using the Host Interface logic. This logic plays a vital role as it can affect the overall performance of the Endpoint device. The Host Interface logic is protocol specific and responsible for the data transfer from host to device and vice versa. Strategically, as this logic is very crucial, it has to be verified properly.There are multiple ways to verify the host interface logic. However, there is a trade-off between design development time (including verification time) and overall cost. In this paper we present a novel approach to verify the Host Interface Logic. Our method uses a PCI Express core that will act as the Root Complex connected to the Host Interface Logic, i.e. Design Under Test (DUT), this will help to minimize overall design development time by reducing verification time.

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Section: Related Workmentioning

confidence: 99%

Accelerating functional verification of PCI express endpoint by emulating host system using PCI express core

Badhe

Kulkarni

Gadre

2014

2014 First International Conference on Computational Systems and Communications (ICCSC)

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“…It is based on OVM version 2.1.1 and is created by Accellera. Its Class Library provides [6] the building blocks needed to quickly develop well-constructed and reusable verification components and test environments. It uses system Verilog as its language and all the major simulation vendor supports it.…”

Section: Introductionmentioning

confidence: 99%

An Introduction to Functional Verification of I2C Protocol using UVM

Kaith¹,

Patel²,

Gupta³

2015

IJCA

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The fabrication technology advancements lead to place more logic on a silicon die which makes verification more challenging task than ever. The large number of resources is required because more than 70% of the design cycle is used for verification. Universal Verification Methodology was developed to provide a well structured and reusable verification environment which does not interfere with the device under test (DUT). This paper contrasts the reusability of I2C using UVM and introduces how the verification environment is constructed and test cases are implemented for this protocol.

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“…Universal Verification Methodology is an open source methodology for using System-Verilog. It is designed mainly for verification IP and testbench components so that testbenches are reusable and verification code is more portable and universal [2] [3]. Each verification component follows a consistent architecture and a complete set of elements for simulating, checking and collecting functional coverage.…”

Section: Introductionmentioning

confidence: 99%

“…SYSTEM VERILOG SystemVerilog (SV) is a special digital hardware verification language used for functional verification of the design. It is a complete object-oriented programming language that includes domain-specific features to support verification [3]. SystemVerilog provides constructs and can be used to simulate the HDL design and verify them by high level test case.…”

Section: Introductionmentioning

confidence: 99%

A Technical Road Map from System Verilog to UVM

Kaith¹

2015

IJRITCC

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Abstract-As the fabrication technology is advancing more logic is being placed on a silicon die which makes verification more challenging task than ever. More than 70% of the design cycle is used for verification. To improve the time to market we need a reusable verification environment that detects all functional errors and avoid re-spin. Universal verification methodology was introduced to fulfill these goals. UVM is well structured, reusable with little or no modifications, do not interfere with the device under test (DUT) and gives the speed of verification. UVM is supported by all major simulator vendors, which was not in earlier methodologies. This methodology provides a standard unified solution that compiles on all tools. This paper introduces the advantages of UVM over System Verilog, basic terminologies used in UVM and a simple functional verification environment construction using UVM.

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Beyond UVM for practical SoC verification

Cited by 56 publications

References 2 publications

Accelerating functional verification of PCI express endpoint by emulating host system using PCI express core

Accelerating functional verification of PCI express endpoint by emulating host system using PCI express core

An Introduction to Functional Verification of I2C Protocol using UVM

A Technical Road Map from System Verilog to UVM

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