Bias-stress induced threshold voltage and drain current instability in 4H–SiC DMOSFETs

Okayama, T.; Arthur, Steve; Garrett, J.L.; Rao, Mulpuri V.

doi:10.1016/j.sse.2007.07.031

Cited by 61 publications

(47 citation statements)

References 16 publications

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“…A typical structure of the SiC DMOS and the reliability issues studied so far are summarized in Fig.10. In addition to the improvement of the interfacial properties at the thermal oxide over SiC, suppression of the shift of the threshold gate voltages after applying high positive or negative voltages has been a critical issue for the reliability [13,14]. Typical data of the shifts are shown in Fig.11.…”

Section: A Structures and Issues Of Sic Transistorsmentioning

confidence: 99%

Reliability issues in GaN and SiC power devices

Ueda

2014

2014 IEEE International Reliability Physics Symposium

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GaN and SiC have been widely investigated for future power switching systems with high efficiencies. So far, prototypes of working transistors using these wide bandgap materials have demonstrated the superior performances suggesting the great potential. Remaining tasks for the commercialization include finding niche applications as entry ones with the well-established reliability. In this paper, recent progress of the GaN and SiC power devices developed at Panasonic is reviewed. After reviewing the reliability issues in the conventional transistors, normally-off GaN Gate Injection Transistors (GITs) and SiC Diode-integrated MOSFET (DioMOS) free from the degradations are presented. These state-of-the-art GaN and SiC devices are very promising for practical applications.

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Section: A Structures and Issues Of Sic Transistorsmentioning

confidence: 99%

Reliability issues in GaN and SiC power devices

Ueda

2014

2014 IEEE International Reliability Physics Symposium

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“…6,7 There are two possible physical origins of BTI phenomena: trapped charges and mobile ions in the oxides. Charge injection into the electrical defects at and/or near poor SiO 2 /SiC interfaces causes BTI typically characterized by a clockwise hysteresis in bidirectional capacitance-voltage (C-V) curves of MOS capacitors.…”

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confidence: 99%

Understanding and controlling bias-temperature instability in SiC metal-oxide-semiconductor devices induced by unusual generation of mobile ions

Chanthaphan

Hosoi

Nakano

et al. 2013

Applied Physics Letters

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Unusual behavior of bias-temperature instabilities in SiC metal-oxide-semiconductor (MOS) devices is studied. Electrical measurements of SiC-MOS capacitors are used to investigate details of self-generated mobile ions in thermal oxides on 4H-SiC(0001) substrates, such as their polarity, density, distribution, and impact on interface properties. It is found that positive bias-temperature stress (BTS) accumulates self-generated positive mobile ions at the bottom SiO2/SiC interface with an areal density of several 1012 cm−2, and that they induce additional electron trap formation at the interface. Using this knowledge, we demonstrate effective removal of the positive mobile ions with a combination of negative BTS and subsequent etching of the oxide surface.

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“…[26][27][28] Due to the dramatic decrease in effective carrier concentration in SiC over the measured temperature range, the sample exhibited V th increase from about 0.73 V at room temperature to 7.4 V at 40 K, as extracted from the x-intercept of the I D versus V GS curve at V DS = 0.1 V. This change in V th indicated a net negative charge of 3 9 10 12 cm À2 present in the oxide. The field-effect mobility (l FE ) decreased from 26.9 cm 2 /V s at room temperature to less than 5 cm 2 /V s below 100 K, as previously reported in the literature.…”

Section: Tsc Spectra Of Mos Transistorsmentioning

confidence: 95%

Spatial Localization of Carrier Traps in 4H-SiC MOSFET Devices Using Thermally Stimulated Current

Tadjer

Stahlbush

Hobart

et al. 2010

Journal of Elec Materi

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Carrier traps in 4H-SiC metal-oxide-semiconductor (MOS) capacitor and transistor devices were studied using the thermally stimulated current (TSC) method. TSC spectra from p-type MOS capacitors and n-channel MOS fieldeffect transistors (MOSFETs) indicated the presence of oxide traps with peak emission around 55 K. An additional peak near 80 K was observed due to acceptor activation and hole traps near the interface. The physical location of the traps in the devices was deduced using a localized electric field approach. The density of hole traps contributing to the 80-K peak was separated from the acceptor trap density using a gamma-ray irradiation method. As a result, hole trap density of N t,hole = 2.08 9 10 15 cm À3 at 2 MV/cm gate field and N t,hole = 2.5 9 10 16 cm À3 at 4.5 MV/cm gate field was extracted from the 80-K TSC spectra. Measurements of the source-body n + -p junction suggested the presence of implantation damage in the space-charge region, as well as defect states near the n + SiC substrate.

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Bias-stress induced threshold voltage and drain current instability in 4H–SiC DMOSFETs

Cited by 61 publications

References 16 publications

Reliability issues in GaN and SiC power devices

Reliability issues in GaN and SiC power devices

Understanding and controlling bias-temperature instability in SiC metal-oxide-semiconductor devices induced by unusual generation of mobile ions

Spatial Localization of Carrier Traps in 4H-SiC MOSFET Devices Using Thermally Stimulated Current

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