BiMDiM: Area efficient Bi-directional MRAM Digital in-Memory Computing

Domain-Specific STT-MRAM-Based In-Memory Computing: A Survey

“…• The scalability of MRIMA to realize complex logic functions may be limited. Kim et al [81] propose BiMDiM, a bi-directional MRAM in-memory computing system that optimizes memory cell size during CNN operations. It reuses memory cells for intermediate sums and carries and uses a re-scheduling technique to reduce inefficient half-additions.…”

“…Cai et al [79] utilized the Spectre simulator in Cadence Virtuoso front-end to simulate the 28 nm CMOS and 40 nm MTJ compact model of their design. Kim et al [81] employed this tool mainly for area estimation of the layout design of the memory cell to perform λ-based design rule to simulate their 28 nm CMOS design. • Synopsys Design Compiler: Like Cadence Virtuoso, Synopsys Design Compiler is a widely used synthesis tool in the field of EDA.…”

“…Proper data organization techniques, such as data compression, data encoding, and data grouping, should be employed to reduce memory footprints, improve data access efficiency, and exploit the parallelism offered by STT-MRAM devices. For instance, Kim et al [81] and Resch et al [74] proposed a memory array design that incorporates the Multiply-Accumulate (MAC) operation. They achieved this by partitioning the memory array into multiple sub-computing arrays, which are utilized for various operations, such as adding partial products and accumulating results.…”