BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel

Lan, Ying-Cherng; Lo, Shih-Hsin; Lin, Yueh-Chi; Hu, Yu-Hen; Chen, Sao-Jie

doi:10.1109/nocs.2009.5071476

Cited by 55 publications

(17 citation statements)

References 10 publications

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“…It is observed that under various traffics, one channel may be full of traffic and another could be idle. The basic concept of BiNoC [12] is switching channel direction to achieve better bandwidth utilization. However, primitive BiNoC architecture only provides good latency results for BE packets because of its better flexibility in the channel utilization, but it is incapable to support critical communication guarantees of GS packets that are much more important for real world applications.…”

Section: F Qos-aware Binocmentioning

confidence: 99%

A novel flow fluidity meter for BiNoC bandwidth resource allocation

Tsai

Lin²,

Lan

et al. 2015

2015 28th IEEE International System-on-Chip Conference (SOCC)

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An enhanced on-chip network resource allocation method is developed for the Bi-directional Network-on-Chip (BiNoC) platform. Specifically, a novel flow Fluidity Meter (FM) is proposed to provide the real-time estimate of bandwidth utilization of the Virtual Channel (VC) buffer in a BiNoC router.The degree of fluidity of a packet transfer in each router is a reliable, yet low-cost method for measuring bandwidth utilization in the VC. We show that the overhead implementing this FM is very affordable. Finally, extensive simulation results verify that this proposed FM approach achieves superior performance compared to existing BiNoC resource allocation methods.

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Section: F Qos-aware Binocmentioning

confidence: 99%

A novel flow fluidity meter for BiNoC bandwidth resource allocation

Tsai

Lin²,

Lan

et al. 2015

2015 28th IEEE International System-on-Chip Conference (SOCC)

Self Cite

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“…RELATED WORK The concept of ShuttleNoC is similar to bandwidth scaling techniques proposed in [15] and [16], in which bi-directional links are employed to resolve low resource utilization. However, they do not target power efficiency in NoCs.…”

Section: Overhead Analysismentioning

confidence: 99%

ShuttleNoC: Boosting on-chip communication efficiency by enabling localized power adaptation

Yan

Wang

et al. 2015

The 20th Asia and South Pacific Design Automation Conference

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Networks-on-Chip (NoC) gradually becomes a main contributor of chip-level power consumption. Due to the temporal and spatial heterogeneity of on-chip traffic, existing power management approaches cannot adapt the NoC power consumption to its traffic intensity, and hence lead to a suboptimal power efficiency. They either resort to over-provisioned NoC design that only suits for traffic spatial distribution, or coarse-grained power gating that only serves traffic temporal variation. In this paper, we propose a novel NoC architecture called Shuttle Networks-on-Chip (ShuttleNoC). By permitting packets shuttling between multiple subnetworks, localized power adaptation can be achieved. Experimental results show that ShuttleNoC could achieve optimal power efficiency with up to 23.5% power savings and 22.3% performance boost in comparison with traditional heterogeneity-agnostic NoC designs.

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“…Additionally, we reverse links/buffers at a coarser granularity to reduce serializer/deserializer overhead. Another reconfigurable design was proposed in BiNoC [21]. BiNoC dynamically reconfigured bidirectional channels to improve performance.…”

Section: Related Workmentioning

confidence: 99%

“…Buffers have been moved from the router to the channels by replacing repeaters on the channel with either flip-flops called elastic buffers load is high or the workload is unbalanced. Recent research on NoC performance has tackled above mentioned problems using techniques such as reversibility or coding schemes [21], [22], [23], [24], [25], [26]. Hesse et al propose a bandwidthadaptive router (BAR) that aims to take advantage of these under-utilized links with bidirectional, adaptive channels [22].…”

Section: Introductionmentioning

confidence: 99%

QORE: A fault tolerant network-on-chip architecture with power-efficient quad-function channel (QFC) buffers

DiTomaso

Kodi

Louri

2014

2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)

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Network-on-Chips (NoCs) are quickly becoming the standard communication paradigm for the growing number of cores on the chip. While NoCs can deliver sufficient bandwidth and enhance scalability, NoCs suffer from high power consumption due to the router microarchitecture and communication channels that facilitate inter-core communication. As technology keeps scaling down in the nanometer regime, unpredictable device behavior due to aging, infant mortality, design defects, soft errors, aggressive design, and process-voltage-temperature variations, will increase and will result in a significant increase in faults (both permanent and transient) and hardware failures. In this paper, we propose QORE -a fault tolerant NoC architecture with Quad-Function Channel (QFC) buffers. The use of QFC buffers and their associated control (link and fault controllers) enhance fault-tolerance by allowing the NoC to dynamically adapt to faults at the link level and reverse propagation direction to avoid faulty links. Additionally, QFC buffers reduce router power and improve performance by eliminating in-router buffering. Our simulation results using real benchmarks and synthetic traffic mixes show that QORE improves speedup by 1.3× and throughput by 2.3× when compared to state-of-the art fault tolerant NoCs designs such as Ariadne and Vicis. Moreover, using Synopsys Design Compiler, we also show that network power in QORE is reduced by 21% with minimal control overhead.

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BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel

Cited by 55 publications

References 10 publications

A novel flow fluidity meter for BiNoC bandwidth resource allocation

A novel flow fluidity meter for BiNoC bandwidth resource allocation

ShuttleNoC: Boosting on-chip communication efficiency by enabling localized power adaptation

QORE: A fault tolerant network-on-chip architecture with power-efficient quad-function channel (QFC) buffers

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