Biodegradation of xylene in a biofilter- effect of process variables, shock loads and kinetic modeling

Biofiltration of methane in presence of ethylbenzene or xylene

“…Xylene-EC increased from 8.0±0.4 to 29.0±2.3 g.m − 3 .h − 1 for X-ILs of 9.0±0.6 to 32.0±0.5 g.m − 3 .h − 1 . The values were close to Natarajan et al (2014) results who obtained X-EC of 9-29 g.m − 3 .h − 1 in a tree-bark BF with ILs varying between 3 and 40 g.m − 3 .h − 1 .…”

“…Lebrero et al (2016) obtained a removal efficiency (RE) close to 90% at a CH 4 -IL of 40 g.m − 3 .h − 1 for a BF packed with compost and inoculated with a pure strain of Graphium sp. Cho et al (2008) obtained an EB-RE of 92% in a rock-compost BF for ILs varying between 10 and 40 g.m − 3 .h − 1 and an EBRT of 62 s. Similar X-REs were obtained by Natarajan et al (2014) in date palm tree bark packed BF for X concentrations between 0.1 and 3 g.m − 3 and an EBRT around 2 min.…”

Junctionless versus inversion-mode lateral semiconductor nanowire transistors

“…Over the past decades, aggressive and continuous transistor scaling according to Moore's law has enabled new system features thanks to ever-increasing device performance and density, reduced cost and power consumption [1][2][3][4][5][6][7][8]. To keep the industry's growth rate, triple-gate finFETs were recently implemented into manufacturing at the 22 nm technology node [2].…”

(Invited) Vertical Nanowire FET Integration and Device Aspects

“…Another etch challenge faced in integration concerns the control of the surface roughness of W when (partially) etching-back this material, namely within the gate-first module of the flow used to build vertical GAA-NWFET devices. W is standardly used as the gate stack fill-metal (2,3,7,8,10,11) but due to its fairly large W grains size, its partial etch-back by a wet (e.g., by ammonium hydroxide-hydrogen peroxide mixture (APM)) or dry (e.g., by a F-based (such as SF6 or NF3) plasma) (34,35) etch process results in a W layer with a quite rough surface, worse if a thicker amount of W material needs to be etched-back. If implementing such processes in the gate-first module of a vertical flow, this will of course bring issues in terms of the control of the gate electrode thickness, and also impact the subsequent isolation layer (its thickness and its surface roughness control) between the gate and top electrodes.…”

“…Over the past decades, aggressive and continuous transistor scaling according to Moore's law has provided ever increasing device performance and density (1)(2)(3). For advanced (sub-)5nm nodes, to keep the growth pace, several options can be considered in terms of material choices, device architectures and circuit designs.…”